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845204AK PDF预览

845204AK

更新时间: 2024-01-07 18:18:31
品牌 Logo 应用领域
艾迪悌 - IDT PC时钟
页数 文件大小 规格书
13页 1102K
描述
CRYSTAL-TO-MLVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM

845204AK 数据手册

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ADVANCE INFORMATION  
CRYSTAL-TO-MLVDS PCI EXPRESS™  
ICS845204  
CLOCK SYNTHESIZER W/SPREAD SPECTRUM  
General Description  
Features  
The ICS845204 is a 4 output PCI Express clock  
Four differential spread spectrum clock outputs  
S
IC  
synthesizer optimized to generate low jitter PCI  
Express™ reference clocks with or without spread  
spectrum modulation and is a member of the  
HiPerClockS™ family of high performance clock  
Each output can be individually disabled by separate  
HiPerClockS™  
output-enable inputs  
Crystal oscillator interface designed for 18pF,  
25MHz parallel resonant crystal  
solutions from IDT. Spread type and amount can be configured via  
the SSC control pins. Using a 25MHz, 18pF parallel resonant  
crystal, the device will generate M-LVDS clocks at either 25MHz,  
100MHz, 125MHz or 250MHz. The ICS845204 uses a low jitter  
VCO that easily meets PCI Express jitter requirements and is  
packaged in a 32-pin VFQFN package.  
Supports the following output frequencies:  
25MHz, 100MHz, 125MHz or 250MHz  
VCO range: 250MHz - 700MHz  
Supports SSC downspread at 0.05% and -0.75%, centerspread  
at 0.25% and no spread options  
Cycle-to-cycle jitter: 50ps (maximum) design target  
Period jitter, RMS: TBD  
Pin Assignment  
Full 3.3V output supply mode  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
nc  
OE0  
24  
23  
22  
21  
20  
nc  
VDD  
nQ3  
Q3  
GND  
Q2  
VDDO  
nQ2  
SSC1  
nc  
nc  
FSEL0  
nc  
19  
18  
17  
GND  
9
10 11 12 13 14 15 16  
Block Diagram  
ICS845204  
0 0 PLL Bypass  
Q0  
32 Lead VFQFN  
5mm x 5mm x 0.925mm  
package body  
25MHz  
nQ0  
XTAL_IN  
Pullup  
Phase  
Detector  
VCO  
250-700MHz  
OE0  
OSC  
0 1 ÷5  
1 0 ÷4  
1 1 ÷2  
K Package  
Top View  
Q1  
XTAL_OUT  
nQ1  
OE1  
Pullup  
Feedback Divider  
Q2  
÷20  
nQ2  
OE2  
Pullup  
Pullup  
2
2
Q3  
Pullup:Pullup  
Spread Spectrum  
Control  
SSC[1:0]  
nQ3  
OE3  
Default = 100MHz  
Pulldown:Pullup  
FSEL[1:0]  
The Advance Information presented herein represents a product that is developmental or prototype. The noted characteristics are design targets. Integrated  
Device Technologies, Inc. (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT™ / ICS™ M-LVDS CLOCK SYNTHESIZER  
1
ICS845204AK SEPTEMBER 25, 2007  

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