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8430S07AKILF

更新时间： 2024-01-14 09:42:39

品牌	Logo	应用领域
艾迪悌 - IDT		晶体时钟发生器微控制器和处理器外围集成电路 PC
页数	文件大小	规格书
26页	881K
描述
Clock Generator for Cavium Processors

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8430S07AKILF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	VFQFPN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.22
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	133.333 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Clock Generators	最大压摆率：	170 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	5 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

8430S07AKILF 数据手册

Clock Generator for Cavium Processors

ICS8430S07I

DATA SHEET

General Description

Features

The ICS8430S07I is a PLL-based clock generator

specifically designed for Cavium Networks SoC

processors. This high performance device is optimized

to generate the processor core reference clock, the

DDR reference clocks, the PCI/PCI-X bus clocks, and

• One selectable differential LVPECL output pair for DDR

533/400/667

HiPerClockS™

• Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance

- One selectable core clock for the processor

- One selectable clock for the PCI/ PCI-X bus

- One 125MHz clock reference for GbE MAC

- Three 25MHz clock references for GbE PHY

the clocks for both the Gigabit Ethernet MAC and PHY. The clock

generator offers ultra low-jitter, low-skew clock outputs, and edge

rates that easily meet the input requirements for the

CN3005/CN3010/CN3020 processors. The output frequencies are

generated from a 25MHz external input source or an external 25MHz

parallel resonant crystal. The extended temperature range of the

ICS8430S07I supports telecommunication, networking, and storage

requirements.

• Selectable external crystal or differential (single-ended) input

source

• Crystal oscillator interface designed for 25MHz, parallel resonant

crystal

• Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,

LVHSTL, SSTL, HCSL input levels

• Internal resistor bias on nCLK pin allows the user to drive CLK

input with external single-ended (LVCMOS/ LVTTL) input levels

• RMS phase jitter @ 125MHz, using a 25MHz crystal

(1.875MHz - 20MHz): 0.78ps (typical), QD output

• Output supply:

LVPECL – 3.3V Core

LVCMOS –Core/Output

3.3V/3.3V

Applications

• Systems using CN30XX MIPS64 Broadband Processors

3.3V/2.5V

• Networking, control and storage equipment, including routers,

switches, application-aware gateways, triple-play gateways,

WLAN and 3G/4G access and aggregation devices, storage

arrays, storage networking equipment, servers, and intelligent

NICs

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• 802.11 a/b/g/n wireless for home data and multi-media distribution

• QoS for high quality Voice, Video, and Data Service

• Next-generation PON, VDSL2, and Cable Networks

• High-performance NAS

Pin Assignment

• Audio/Video Storage and Distribution

• Consumer Space Media Server

32 31 30 29 28 27 26 25

V_{DDO_C}

V_DD

23 QC

ICS8430S07I

nPLL_SEL

XTAL_IN

CORE_SEL

32-Lead VFQFN

5mm x 5mm x 0.925mm

package body

GND

XTAL_OUT

nXTAL_SEL

20 GND

K Package

CLK

nCLK

GND

MR/ nOE_REF

Top View

17 V_{DDO_B}

14 15 16

10 11 12

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009

12 3 4 5 6 7...26

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