5秒后页面跳转
843002AKI-40 PDF预览

843002AKI-40

更新时间: 2024-02-10 11:13:16
品牌 Logo 应用领域
艾迪悌 - IDT 石英晶振压控振荡器衰减器
页数 文件大小 规格书
23页 1180K
描述
175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

843002AKI-40 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD, VFQFN-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.86
Is Samacsys:N其他特性:IT ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码:S-XQCC-N32JESD-609代码:e0
长度:5 mm湿度敏感等级:3
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:175 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):225
电源:2.5/3.3 V主时钟/晶体标称频率:19.44 MHz
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Generators最大压摆率:210 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

843002AKI-40 数据手册

 浏览型号843002AKI-40的Datasheet PDF文件第2页浏览型号843002AKI-40的Datasheet PDF文件第3页浏览型号843002AKI-40的Datasheet PDF文件第4页浏览型号843002AKI-40的Datasheet PDF文件第5页浏览型号843002AKI-40的Datasheet PDF文件第6页浏览型号843002AKI-40的Datasheet PDF文件第7页 
TM  
175MHZ, FEMTOCLOCK VCXO BASED  
ICS843002I-40  
SONET/SDH JITTER ATTENUATOR  
General Description  
Features  
The ICS843002I-40 is a member of the  
Two Differential LVPECL outputs  
S
IC  
HiperClockS™ family of high performance clock  
solutions from IDT. The ICS843002I-40 is a PLL  
based synchronous clock generator that is  
Selectable CLKx, nCLKx differential input pairs  
HiPerClockS™  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or  
single-ended LVCMOS or LVTTL levels  
optimized for SONET/SDH line card applications  
where jitter attenuation and frequency translation is needed. The  
device contains two internal PLL stages that are cascaded in  
series. The first PLL stage uses a VCXO which is optimized to  
provide reference clock jitter attenuation and to be jitter tolerant,  
and to provide a stable reference clock for the 2nd PLL stage  
(typically 19.44MHz). The second PLL stage provides additional  
frequency multiplication (x32), and it maintains low output jitter by  
using a low phase noise FemtoClock VCO. PLL multiplication  
ratios are selected from internal lookup tables using device input  
selection pins. The device performance and the PLL multiplication  
ratios are optimized to support non-FEC (non-Forward Error  
Correction) SONET/SDH applications with rates up to OC-48  
(SONET) or STM-16 (SDH). The VCXO requires the use of an  
external, inexpensive pullable crystal. VCXO PLL uses external  
passive loop filter components which are used to optimize the PLL  
loop bandwidth and damping characteristics for the given  
line card application.  
Maximum output frequency: 175MHz  
FemtoClock VCO frequency range: 560MHz - 700MHz  
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal  
(12kHz to 20MHz): 0.81ps (typical)  
Full 3.3V or mixed 3.3V core/2.5V output operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
The ICS843002I-40 includes two clock input ports. Each one can  
accept either a single-ended or differential input. Each input port  
also includes an activity detector circuit, which reports input clock  
activity through the LOR0 and LOR1 logic output pins. The two  
input ports feed an input selection mux. “Hitless switching” is  
accomplished through proper filter tuning. Jitter transfer and  
wander characteristics are influenced by loop filter tuning, and  
phase transient performance is influenced by both loop filter  
tuning and alignment error between the two reference clocks.  
32 31 30 29 28 27 26 25  
1
2
3
24  
23  
22  
LF1  
LF0  
LOR0  
LOR1  
nc  
ISET  
Typical ICS843002I-40 configuration in SONET/SDH Systems:  
VCXO 19.44MHz crystal  
VCC  
VCCO_LVCMOS  
VCCO_LVPECL  
nQB  
4
5
21  
20  
CLK0  
nCLK0  
CLK_SEL  
nc  
6
7
8
19  
18  
17  
QB  
Loop bandwidth: 50Hz - 250Hz  
VEE  
Input Reference clock frequency selections:  
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,  
622.08MHz  
9
10 11 12 13 14 15 16  
Output clock frequency selections:  
19.44MHz, 77.76MHz, 155.52MHz, Hi-Z  
ICS843002I-40  
32-Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
Top View  
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR  
1
ICS843002AKI-40 REV. A NOVEMBER 7, 2007  

与843002AKI-40相关器件

型号 品牌 描述 获取价格 数据表
843002AKI-40LF IDT 175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

获取价格

843002AKI-40LFT IDT 175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

获取价格

843002AKI-40T IDT 175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

获取价格

843002AKI-41 IDT 700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

获取价格

843002AKI-41LF IDT 700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

获取价格

843002AKI-41LFT IDT 700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

获取价格