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841N254AKI PDF预览

841N254AKI

更新时间: 2024-01-31 16:38:09
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
23页 480K
描述
FEMTOCLOCK? NG Crystal-to-LVDS/HCSL Clock Synthesizer

841N254AKI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.33
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/1912205.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=1912205
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=19122053D View:https://componentsearchengine.com/viewer/3D.php?partID=1912205
Samacsys PartID:1912205Samacsys Image:https://componentsearchengine.com/Images/9/841N254BKILFT.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/841N254BKILFT.jpgSamacsys Pin Count:33
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:NLG32P1Samacsys Released Date:2020-01-19 15:35:53
Is Samacsys:N其他特性:ALSO OPERATES AT 3.3 V SUPPLY
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:250 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:25 MHz
座面最大高度:1 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

841N254AKI 数据手册

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®
ICS841N254I  
FEMTOCLOCK NG  
Crystal-to-LVDS/HCSL Clock Synthesizer  
DATA SHEET  
General Description  
Features  
The ICS841N254I is a 4-output clock synthesizer designed for S-RIO  
1.3 and 2.0 reference clock applications. The device generates four  
copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz  
clock signal with excellent phase jitter performance. The four outputs  
are organized in two banks of two LVDS and two HCSL ouputs.The  
device uses IDT’s fourth generation FemtoClock® NG technology for  
an optimum of high clock frequency and low phase noise  
performance, combined with a low power consumption and high  
power supply noise rejection. The synthesized clock frequency and  
the phase-noise performance are optimized for driving RIO 1.3 and  
2.0 SerDes reference clocks. The device supports 3.3V and 2.5V  
voltage supplies and is packaged in a small 32-lead VFQFN  
package. The extended temperature range supports wireless  
infrastructure, telecommunication and networking end equipment  
requirements.  
Fourth generation FemtoClock® (NG) technology  
Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output  
clock synthesized from a 25MHz fundamental mode crystal  
Four differential clock outputs (two LVDS and two HCSL outputs)  
Crystal interface designed for 25MHz,  
parallel resonant crystal  
RMS phase jitter @ 156.25MHz, using a 25MHz crystal  
(1MHz - 20MHz): 0.27ps (typical)  
RMS phase jitter @ 156.25MHz, using a 25MHz crystal  
(12kHz - 20MHz): 0.32ps (typical)  
Power supply noise rejection PSNR: -50dB (typical)  
LVCMOS interface levels for the frequency select input  
Full 3.3V or 2.5V supply voltage  
Available in both standard (RoHS 5) and Lead-free (RoHS 6)  
packages  
-40°C to 85°C ambient operating temperature  
Function Table  
Inputs  
Pin Assignment  
Output Frequency with  
F_SEL1  
F_SEL0  
fXTAL = 25MHz  
156.25MHz  
125MHz  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
VDD  
IREF  
24  
23  
22  
21  
20  
0 (default)  
0 (default)  
nc  
VDDA  
GND  
nQA0  
QA0  
0
1
1
1
0
1
ICS841N254I  
32-lead VFQFN  
K Package  
100MHz  
nc  
250MHz  
5mm x 5mm x 0.925mm  
package body  
VDDOA  
GND  
REF_CLK  
nOEA  
VDD  
nQA1  
QA1  
19  
18  
17  
NOTE: F_SEL[1:0] are asynchronous controls.  
Top View  
GND  
9
10 11 12 13 14 15 16  
Block Diagram  
QA0  
nQA0  
XTAL_IN  
LVDS  
LVDS  
HCSL  
HCSL  
1
0
OSC  
0
1
÷N  
XTAL_OUT  
REF_CLK  
PFD  
&
LPF  
FemtoClock® NG  
VCO  
QA1  
nQA1  
Pulldown  
625MHz  
QB0  
nQB0  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
÷25  
REF_SEL  
BYPASS  
F_SEL[0:1]  
nOEA  
2
QB1  
nQB1  
nOEB  
IREF  
ICS841N254AKI REVISION A APRIL 18, 2011  
1
©2011 Integrated Device Technology, Inc.  

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