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82V3001PV PDF预览

82V3001PV

更新时间: 2024-01-12 04:27:03
品牌 Logo 应用领域
艾迪悌 - IDT 输入元件
页数 文件大小 规格书
27页 370K
描述
Clock Generator, PDSO56

82V3001PV 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:SSOP, SSOP56,.4Reach Compliance Code:not_compliant
风险等级:5.92Is Samacsys:N
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
湿度敏感等级:1端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH电源:3.3 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:50 mA标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

82V3001PV 数据手册

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WAN PLL WITH SINGLE  
REFERENCE INPUT  
IDT82V3001A  
FEATURES  
Attenuates wander from 2.1 Hz  
Fast Lock mode  
Provides Time Interval Error (TIE) correction  
MTIE of 600 ns  
Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra-  
tum 4 Enhanced and Stratum 4 timing for DS1 interfaces  
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim-  
ing for E1 interface  
Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048  
MHz  
Provides eight types of clock signals: C1.5o, C3o, C2o, C4o,  
C6o, C8o, C16o and C32o  
Provides six types of 8 kHz framing pulses: F0o, F8o, F16o,  
F32o, RSP and TSP  
JTAG boundary scan  
Holdover status indication  
Freerun status indication  
Normal status indication  
Lock status indication  
3.3 V operation with 5 V tolerant I/O  
Package available: 56-pin SSOP  
Holdover frequency accuracy of 0.025 ppm  
Phase slope of 5 ns/125 µs  
DESCRIPTION  
The IDT82V3001A is a WAN PLL with single reference input. It  
contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS  
clocks and framing signals that are phase locked to a 2.048 MHz, 1.544  
MHz or 8 kHz input reference.  
meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/  
wander, frequency accuracy, capture range, phase change slope,  
holdover frequency accuracy and MTIE (Maximum Time Interval Error)  
requirements for these specifications.  
The IDT82V3001A provides eight types of clock signals (C1.5o, C3o,  
C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o,  
F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate  
transmission links.  
The IDT82V3001A is compliant with AT&T TR62411, Telcordia GR-  
1244-CORE Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011. It  
The IDT82V3001A can be used in synchronization and timing control  
for T1 and E1 systems, or used as ST-BUS clock and frame pulse  
sources. It can also be used in access switch, access routers, ATM edge  
switches, wireless base station controllers, or IADs (Integrated Access  
Devices), PBXs and line cards.  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
OCTOBER 22, 2003  
INDUSTRIAL TEMPERATURE RANGE  
1
DSC-6242/2  
2003 Integrated Device Technology, Inc.  

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