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813322BK-02T PDF预览

813322BK-02T

更新时间: 2024-02-19 18:56:19
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路石英晶振压控振荡器衰减器
页数 文件大小 规格书
20页 374K
描述
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER

813322BK-02T 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
Is Samacsys:NJESD-30 代码:S-XQCC-N32
JESD-609代码:e0长度:5 mm
端子数量:32最高工作温度:70 °C
最低工作温度:最大输出时钟频率:622.08 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225主时钟/晶体标称频率:156.25 MHz
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

813322BK-02T 数据手册

 浏览型号813322BK-02T的Datasheet PDF文件第2页浏览型号813322BK-02T的Datasheet PDF文件第3页浏览型号813322BK-02T的Datasheet PDF文件第4页浏览型号813322BK-02T的Datasheet PDF文件第5页浏览型号813322BK-02T的Datasheet PDF文件第6页浏览型号813322BK-02T的Datasheet PDF文件第7页 
PRELIMINARY  
VCXO JITTER ATTENUATOR &  
FEMTOCLOCK™ MULTIPLIER  
ICS813322-02  
GENERAL DESCRIPTION  
FEATURES  
Two differential LVPECL outputs  
The ICS813322-02 is  
a member of the  
Each output supports independent frequency selection at  
19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz  
ICS  
HiperClockSfamily of high performance clock  
solutions from IDT. The ICS813322-02 is a PLL  
based synchronous multiplier that is optimized for  
Ethernet or SONET-to-SONET clock jitter atten-  
HiPerClockS™  
Two differential inputs support the following input types:  
LVPECL, LVDS, HCSL  
uation and frequency translation. The device contains two  
internal frequency multiplication stages that are cascaded in  
series.The first stage is a VCXO PLL that is optimized to provide  
reference clock jitter attenuation. The second stage is a  
FemtoClock™ frequency multiplier that provides the low jitter,  
high frequency SONET output clock that meets up to SONET  
OC-48 jitter requirements. Pre-divider and output divider  
multiplication ratios are selected using device selection  
control pins. The multiplication ratios are optimized to support  
most common clock rates used in Ethernet and SONET  
applications. The VCXO requires the use of an external,  
inexpensive pullable crystal. The VCXO uses external passive  
loop filter components which allows configuration of the PLL  
loop bandwidth and damping characteristics. The device is  
packaged in a space-saving 32-VFQFN package.  
Accepts input frequencies from 8kHz to 156.25MHz including  
8kHz,19.44MHz, 25MHz, 62.5MHZ, 77.76MHz, 125MHz,  
155.52MHz and 156.25MHz  
Each output has independently controlled dividers for  
common SONET clock rates  
Attenuates the phase jitter of the input clock by using a low-  
cost pullable funamental mode VCXO crystal  
VCXO PLL bandwidth can be optimized for jitter attenuation  
and reference tracking using external loop filter connection  
FemtoClock frequency multiplier provides low jitter, high  
frequency output  
Absolute pull range: 50ppm  
FemtoClock VCO frequency: 622.08MHz  
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal  
(12kHz – 20MHz): 1.16ps (typical)  
PIN ASSIGNMENT  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
32 31 30 29 28 27 26 25  
LF1  
LF0  
1
2
3
4
5
6
7
8
VEE  
24  
23  
22  
21  
20  
19  
18  
17  
nQB  
QB  
ISET  
VEE  
VCCO  
nQA  
QA  
ICS813322-02  
CLK_SEL  
VCC  
nc  
VEE  
VEE  
ODASEL_0  
9 10 11 12 13 14 15 16  
32-Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
Top View  
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization  
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT/ ICSVCXO JITTER ATTENUATOR/MULTIPLIER  
1
ICS813322BK-02 REV. B AUGUST 14, 2008  

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