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74FCT388915T70PY

更新时间： 2024-02-22 23:20:26

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
10页	154K
描述
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

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74FCT388915T70PY 数据手册

IDT74FCT388915T

3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)

COMMERCIALTEMPERATURERANGE

3.3V LOW SKEW PLL-BASED

CMOS CLOCK DRIVER

(WITH 3-STATE)

IDT74FCT388915T

70/100/133/150

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

The FCT388915T uses phase-lock loop technology to lock the fre-

quencyandphase ofoutputs tothe inputreference clock. Itprovides low

skewclockdistributionforhighperformancePCsandworkstations. Oneof

the outputs is fed back to the PLL at the FEEDBACK input resulting in

essentiallyzerodelayacross the device. The PLLconsists ofthe phase/

frequency detector, charge pump, loop filter and VCO. The VCO is

designed for a 2Q operating frequency range of 40MHz to f2Q Max.

TheFCT388915Tprovides8outputs,theQ5outputisinvertedfromthe

Qoutputs. The 2Qruns attwice the QfrequencyandQ/2runs athalfthe

Qfrequency.

• Input frequency range: 10MHz – f2Q Max. spec

(FREQ_SEL = HIGH)

• Max. output frequency: 150MHz

• Pin and function compatible with FCT88915T, MC88915T

• 5 non-inverting outputs, one inverting output, one 2x output,

one ÷2 output; all outputs are TTL-compatible

• 3-State outputs

• Duty cycle distortion < 500ps (max.)

• 32/–16mA drive at CMOS output voltage levels

• VCC = 3.3V ± 0.3V

The FREQ_SELcontrolprovides anadditional÷2optioninthe output

path. PLL _EN allows bypassing of the PLL, which is useful in static test

modes. WhenPLL_ENis low,SYNCinputmaybe usedas a testclock. In

this testmode,theinputfrequencyis notlimitedtothespecifiedrangeand

thepolarityofoutputsiscomplementarytothatinnormaloperation(PLL_EN

=1). The LOCKoutputattains logicHIGHwhenthe PLLis insteady-state

phase andfrequencylock. WhenOE/RST is low,allthe outputs are putin

highimpedance state andregisters atQ,Q andQ/2outputs are reset.

The FCT388915T requires one external loop filter component as

recommended in Figure 3.

• Inputs can be driven by 3.3V or 5V components

• Available in 28 pin PLCC and SSOP packages

FUNCTIONALBLOCKDIAGRAM

FEEDBACK

LOCK

Voltage

Controlled

Oscilator

Phase/Freq.

Detector

0 M

Charge Pump

SYNC (0)

SYNC (1)

REF_SEL

PLL_EN

Mux

(÷1)

(÷2)

Divide

-By-2

FREQ_SEL

OE/RST

Q/2

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

OCTOBER 2008

DSC-4243/7

12 3 4 5 6 7...10

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