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74FCT388915T100PYG PDF预览

74FCT388915T100PYG

更新时间: 2024-02-23 12:22:33
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器
页数 文件大小 规格书
10页 154K
描述
PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, GREEN, SSOP-28

74FCT388915T100PYG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:GREEN, SSOP-28针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.68Is Samacsys:N
其他特性:OUTPUT FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F; MAX PART TO PART SKEW = 1NS系列:FCT
输入调节:SCHMITT TRIGGER MUXJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.032 A
湿度敏感等级:1功能数量:1
反相输出次数:1端子数量:28
实输出次数:7最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V传播延迟(tpd):1.3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.8 ns
座面最大高度:1.99 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
最小 fmax:100 MHzBase Number Matches:1

74FCT388915T100PYG 数据手册

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3.3V LOW SKEW PLL-BASED  
CMOS CLOCK DRIVER  
(WITH 3-STATE)  
IDT74FCT388915T  
70/100/133/150  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
The FCT388915T uses phase-lock loop technology to lock the fre-  
quencyandphase ofoutputs tothe inputreference clock. Itprovides low  
skewclockdistributionforhighperformancePCsandworkstations. Oneof  
the outputs is fed back to the PLL at the FEEDBACK input resulting in  
essentiallyzerodelayacross the device. The PLLconsists ofthe phase/  
frequency detector, charge pump, loop filter and VCO. The VCO is  
designed for a 2Q operating frequency range of 40MHz to f2Q Max.  
TheFCT388915Tprovides8outputs,theQ5outputisinvertedfromthe  
Qoutputs. The 2Qruns attwice the QfrequencyandQ/2runs athalfthe  
Qfrequency.  
Input frequency range: 10MHz – f2Q Max. spec  
(FREQ_SEL = HIGH)  
Max. output frequency: 150MHz  
• Pin and function compatible with FCT88915T, MC88915T  
• 5 non-inverting outputs, one inverting output, one 2x output,  
one ÷2 output; all outputs are TTL-compatible  
• 3-State outputs  
Duty cycle distortion < 500ps (max.)  
• 32/–16mA drive at CMOS output voltage levels  
VCC = 3.3V ± 0.3V  
The FREQ_SELcontrolprovides anadditional÷2optioninthe output  
path. PLL _EN allows bypassing of the PLL, which is useful in static test  
modes. WhenPLL_ENis low,SYNCinputmaybe usedas a testclock. In  
this testmode,theinputfrequencyis notlimitedtothespecifiedrangeand  
thepolarityofoutputsiscomplementarytothatinnormaloperation(PLL_EN  
=1). The LOCKoutputattains logicHIGHwhenthe PLLis insteady-state  
phase andfrequencylock. WhenOE/RST is low,allthe outputs are putin  
highimpedance state andregisters atQ,Q andQ/2outputs are reset.  
The FCT388915T requires one external loop filter component as  
recommended in Figure 3.  
Inputs can be driven by 3.3V or 5V components  
Available in 28 pin PLCC and SSOP packages  
FUNCTIONALBLOCKDIAGRAM  
FEEDBACK  
LOCK  
Voltage  
Controlled  
Oscilator  
Phase/Freq.  
Detector  
0 M  
u
Charge Pump  
SYNC (0)  
SYNC (1)  
x
1
LF  
REF_SEL  
PLL_EN  
0
1
2Q  
Mux  
(÷1)  
(÷2)  
1
0
M
u
x
D
Q0  
Q1  
Q
CP  
Q
R
R
R
R
R
R
R
Divide  
-By-2  
D
Q
Q
Q
Q
Q
Q
FREQ_SEL  
OE/RST  
CP  
D
Q2  
Q3  
CP  
D
CP  
D
Q4  
Q5  
Q/2  
CP  
D
CP  
D
CP  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 2008  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4243/7  

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