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7133SA55J PDF预览

7133SA55J

更新时间: 2024-01-17 05:20:08
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
17页 311K
描述
PLCC-68, Tube

7133SA55J 技术参数

生命周期:Active包装说明:QFP,
Reach Compliance Code:compliant风险等级:5.59
Is Samacsys:N最长访问时间:90 ns
JESD-30 代码:S-PQFP-G100内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端子数量:100
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:2KX16
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL筛选级别:MIL-PRF-38535
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

7133SA55J 数据手册

 浏览型号7133SA55J的Datasheet PDF文件第2页浏览型号7133SA55J的Datasheet PDF文件第3页浏览型号7133SA55J的Datasheet PDF文件第4页浏览型号7133SA55J的Datasheet PDF文件第5页浏览型号7133SA55J的Datasheet PDF文件第6页浏览型号7133SA55J的Datasheet PDF文件第7页 
IDT7133SA/LA  
IDT7143SA/LA  
HIGH SPEED  
2K X 16 DUAL-PORT  
SRAM  
Features  
High-speed access  
MASTER IDT7133 easily expands data bus width to 32 bits  
or more using SLAVE IDT7143  
Military:35/55/70/90ns(max.)  
Industrial:25/55ns(max.)  
Commercial:20/25/35/45/55/70/90ns(max.)  
On-chip port arbitration logic (IDT7133 only)  
BUSY output flag on IDT7133; BUSY input on IDT7143  
Fully asynchronous operation from either port  
Battery backup operation–2V data retention  
TTL-compatible; single 5V (±10%) power supply  
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-  
pin TQFP  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Low-power operation  
IDT7133/43SA  
Active:1150mW(typ.)  
Standby: 5mW (typ.)  
IDT7133/43LA  
Active:1050mW(typ.)  
Standby: 1mW (typ.)  
Versatile control for write: separate write control for lower  
and upper byte of each port  
Green parts available, see ordering information  
Functional Block Diagram  
R/WRUB  
R/WLUB  
CER  
CE  
L
R/WLLB  
R/WRLB  
OE  
R
OE  
L
I/O8L - I/O15L  
I/O0L - I/O7L  
(1)  
I/O8R - I/O15R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0R - I/O7R  
(1)  
R
BUSY  
BUSY  
L
A
10R  
A
10L  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
0L  
A
0R  
11  
11  
ARBITRATION  
LOGIC  
CE  
R
CE  
L
(IDT7133 ONLY)  
2746 drw 01  
NOTE:  
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.  
IDT7143 (SLAVE): BUSY is input.  
JANUARY 2012  
1
DSC 2746/14  
©2013IntegratedDeviceTechnology,Inc.  

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