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663MLF

更新时间: 2024-02-16 17:08:57
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 218K
描述
PLL BUILDING BLOCK Phase detector and VCO blocks can be used Lower power CMOS process

663MLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOIC-8针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
Is Samacsys:N系列:663
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3.13 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mm最小 fmax:120 MHz
Base Number Matches:1

663MLF 数据手册

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DATASHEET  
PLL BUILDING BLOCK  
ICS663  
Description  
Features  
The ICS663 is a low cost Phase-Locked Loop (PLL)  
designed for clock synthesis and synchronization. Included  
on the chip are the phase detector, charge pump, Voltage  
Controlled Oscillator (VCO) and an output buffer. Through  
the use of external reference and VCO dividers  
(implemented with the ICS674-01, for example), the user  
can easily configure the device to lock to a wide variety of  
input frequencies.  
Packaged in 8-pin SOIC (Pb free)  
Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to  
120 MHz (5 V)  
External PLL loop filter enables configuration for a wide  
range of input frequencies  
Ability to accept an input clock in the kHz range (video  
Hsync, for example)  
25 mA output drive capability at TTL levels  
Lower power CMOS process  
The phase detector and VCO functions of the device can  
also be used independently. This enables the configuration  
of other PLL circuits. For example, the ICS663 phase  
detector can be used to control a VCXO circuit such as the  
MK3754.  
+3.3 V 5ꢀ or +5 V 10ꢀ operating voltage  
Used along with the ICS674-01, forms a complete PLL  
circuit  
Phase detector and VCO blocks can be used  
For applications requiring Power Down or Output Enable  
features, please refer to the ICS673-01.  
independently for other PLL configurations  
Industrial temperature version available  
For better jitter performance, use the MK1575  
Block Diagram  
LF  
LFR  
VDD  
Icp  
UP  
REFIN  
Clock Input  
Phase/  
1
Frequency  
Detector  
VCO  
MUX  
0
2
CLK  
DOWN  
FBIN  
4
Icp  
SEL  
External Feedback Divider  
(such as the ICS674-01)  
IDT™ / ICS™ PLL BUILDING BLOCK  
1
ICS663  
REV E 012006  

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