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5V9885TNLGI8 PDF预览

5V9885TNLGI8

更新时间: 2024-01-15 02:51:11
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
39页 513K
描述
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

5V9885TNLGI8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:VFQFPN
包装说明:QCCN, LCC28,.24SQ,25针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/730035.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=730035
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=7300353D View:https://componentsearchengine.com/viewer/3D.php?partID=730035
Samacsys PartID:730035Samacsys Image:https://componentsearchengine.com/Images/9/5V9885TNLGI8.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/5V9885TNLGI8.jpgSamacsys Pin Count:29
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:nlg28Samacsys Released Date:2020-01-16 10:43:20
Is Samacsys:NJESD-30 代码:S-XQCC-N28
JESD-609代码:e3长度:6.3 mm
湿度敏感等级:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:500 MHz封装主体材料:UNSPECIFIED
封装代码:QCCN封装等效代码:LCC28,.24SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:400 MHz认证状态:Not Qualified
子类别:Clock Generators最大压摆率:110 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

5V9885TNLGI8 数据手册

 浏览型号5V9885TNLGI8的Datasheet PDF文件第2页浏览型号5V9885TNLGI8的Datasheet PDF文件第3页浏览型号5V9885TNLGI8的Datasheet PDF文件第4页浏览型号5V9885TNLGI8的Datasheet PDF文件第5页浏览型号5V9885TNLGI8的Datasheet PDF文件第6页浏览型号5V9885TNLGI8的Datasheet PDF文件第7页 
IDT5V9885T  
3.3V EEPROM  
PROGRAMMABLE CLOCK  
GENERATOR  
FEATURES:  
DESCRIPTION:  
• Three internal PLLs  
TheIDT5V9885Tisaprogrammableclockgeneratorintendedforhigh  
performancedata-communications,telecommunications,consumer,and  
networking applications. There are three internal PLLs, each individually  
programmable,allowingforthreeuniquenon-integer-relatedfrequencies.  
The frequencies are generated from a single reference clock. The  
reference clock can come from one of the two redundant clock inputs. A  
glitchless automatic or manual switchover function allows any one of the  
redundant clocks to be selected during normal operation.  
• Internal non-volatile EEPROM  
• JTAG and FAST mode I2C serial interfaces  
• Input Frequency Ranges: 1MHz to 400MHz  
• Output Frequency Ranges: 4.9kHz to 500MHz  
• Reference Crystal Input with programmable oscillator gain and  
programmable linear load capacitance  
Crystal Frequency Range: 8MHz to 50MHz  
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider  
• 10-bit post-divider blocks  
The IDT5V9885T can be programmed through the use of the I2C or  
JTAG interfaces. The programming interface enables the device to be  
programmedwhenitisinnormaloperationorwhatiscommonlyknownas  
in-system programmable. An internal EEPROM allows the user to save  
and restore the configuration of the device without having to reprogram it  
on power-up. JTAG boundary scan is also implemented.  
• Fractional Dividers  
• Two of the PLLs support Spread Spectrum Generation  
capability  
• I/O Standards:  
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS  
Inputs - 3.3V LVTTL/ LVCMOS  
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback  
divider. Thisallowstheusertogeneratethreeuniquenon-integer-related  
frequencies. The PLL loop bandwidth is programmable to allow the user  
totailorthePLLresponsetotheapplication. Forinstance,theusercantune  
the PLL parameters to minimize jitter generation or to maximize jitter  
attenuation. Spread spectrum generation and fractional divides are  
allowed on two of the PLLs.  
• Programmable Slew Rate Control  
• Programmable Loop Bandwidth Settings  
• Programmable output inversion to reduce bimodal jitter  
• Redundant clock inputs with glitchless auto and manual  
switchover options  
• JTAG Boundary Scan  
• Individual output enable/disable  
• Power-down mode  
Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe  
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The  
otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs  
via the switch matrix. The switch matrix allows the user to route the PLL  
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize  
the board layout. In addition, each output's slew rate and enable/disable  
function can be programmed.  
• 3.3VVDD  
• Available in TQFP and VFQFPN packages  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
SEPT. 2011  
1
c
2011 Integrated Device Technology, Inc.  
DSC 7117/4  

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