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5T995PFI PDF预览

5T995PFI

更新时间: 2024-01-19 08:04:38
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动时钟驱动器
页数 文件大小 规格书
10页 120K
描述
Clock Driver, PQFP44

5T995PFI 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:QFP, QFP44,.47SQ,32Reach Compliance Code:unknown
风险等级:5.84Is Samacsys:N
JESD-30 代码:S-PQFP-G44JESD-609代码:e3
最大I(ol):0.012 A湿度敏感等级:3
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK
电源:2.5 V认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
Base Number Matches:1

5T995PFI 数据手册

 浏览型号5T995PFI的Datasheet PDF文件第2页浏览型号5T995PFI的Datasheet PDF文件第3页浏览型号5T995PFI的Datasheet PDF文件第4页浏览型号5T995PFI的Datasheet PDF文件第5页浏览型号5T995PFI的Datasheet PDF文件第6页浏览型号5T995PFI的Datasheet PDF文件第7页 
2.5V PROGRAMMABLE  
IDT5T995/A  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™ II  
FEATURES:  
DESCRIPTION:  
• Ref input is 3.3V tolerant  
The IDT5T995 is a high fanout 2.5V PLL based clock driver intended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
theREFinputsignal.TheIDT5T995haseightprogrammableskewoutputs  
in four banks of 2. Skew is controlled by 3-level input signals that may be  
hard-wired to appropriate high-mid-low levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 185ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Input frequency:  
– Std: 2MHz to 160MHz  
– A: 2MHz to 200MHz  
• Output frequency:  
– Std: 6MHz to 160MHz  
The feedback input allows divide-by-functionality from 1 to 12 through  
the use of the DS[1:0] inputs. This provides the user with frequency  
multiplication from 1 to 12 without using divided outputs for feedback.  
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.  
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are  
synchronouslydisabled. TheLOCKoutputassertstoindicatewhenPhase  
Lock has been achieved.  
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith  
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs  
are synchronized with the negative edge of REF. The IDT5T995 has  
LVTTL outputs with 12mA balanced drive outputs.  
– A: 6MHz to 200MHz  
• 3-level inputs for skew and PLL range control  
• 3-level inputs for feedback divide selection multiply / divide  
ratios of (1-6, 8, 10, 12) / (2, 4)  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Power-down mode  
• Lock indicator  
• Standard and A speed grades  
• Available in TQFP package  
PE TEST  
FS LOCK  
FUNCTIONALBLOCKDIAGRAM  
PD  
sOE  
3
3
REF  
FB  
PLL  
/ N  
3
3
DS1:0  
1F1:0  
1Q0  
1Q1  
3
3
Skew  
Select  
3
3
2Q0  
2Q1  
Skew  
2F1:0  
3F1:0  
4F1:0  
Select  
3
3
3Q0  
3Q1  
Skew  
Select  
3
3
4Q0  
4Q1  
Skew  
Select  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
DECEMBER 2006  
1
c
2006 Integrated Device Technology, Inc.  
DSC 5850/7  

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