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5P49EE502NDGI PDF预览

5P49EE502NDGI

更新时间: 2024-01-26 01:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
26页 233K
描述
VERSACLOCK? LOW POWER CLOCK GENERATOR IDT5P49EE502

5P49EE502NDGI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Not Recommended零件包装代码:VFQFPN
包装说明:HVQCCN, LCC20,.11SQ,16针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.86
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/11129316.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=11129316
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=111293163D View:https://componentsearchengine.com/viewer/3D.php?partID=11129316
Samacsys PartID:11129316Samacsys Image:https://componentsearchengine.com/Images/9/5P49EE502NDGI.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/5P49EE502NDGI.jpgSamacsys Pin Count:21
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:NDG20P2*Samacsys Released Date:2020-01-21 04:24:16
Is Samacsys:NJESD-30 代码:S-XQCC-N20
JESD-609代码:e3长度:3 mm
湿度敏感等级:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:120 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC20,.11SQ,16
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:1.8 V
主时钟/晶体标称频率:40 MHz认证状态:Not Qualified
座面最大高度:1 mm子类别:Clock Generators
最大供电电压:1.98 V最小供电电压:1.62 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

5P49EE502NDGI 数据手册

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DATASHEET  
VERSACLOCK® LOW POWER CLOCK GENERATOR  
IDT5P49EE502  
Description  
Features  
The IDT5P49EE502 is a programmable clock generator  
intended for low power, battery operated consumer  
applications. There are four internal PLLs, each individually  
programmable, allowing for up to five differrent output  
frequencies. The frequencies are generated from a single  
reference clock. The reference clock can come from either  
a TCXO or fundamental mode crystal.  
Four internal PLLs  
Internal non-volatile EEPROM  
2
Internal I C EEPROM master interface  
2
FAST (400kHz) mode I C serial interfaces  
Input Frequencies  
– TCXO: 10 MHz to 40 MHz  
– Crystal: 8 MHz to 30 MHz  
The IDT5P49EE502 can be programmed through the use  
2
of the I C interfaces. The programming interface enables  
Output Frequency Ranges: kHz to 120 MHz  
the device to be programmed when it is in normal operation  
or what is commonly known as in system programmable.  
An internal EEPROM allows the user to save and restore  
the configuration of the device without having to reprogram  
it on power-up.  
Each PLL has an 8-bit reference divider and a 11-bit  
feedback-divider  
8-bit output-divider blocks  
One of the PLLs support Spread Spectrum generation  
capable of configuration to pixel rate, with adjustable  
modulation rate and amplitude to support video clock  
with no visible artifacts  
Each of the four PLLs has an 8-bit reference divider and a  
11-bit feedback divider. This allows the user to generate  
four unique non-integer-related frequencies. The PLL loop  
bandwidth is programmable to allow the user to tailor the  
PLL response to the application. For instance, the user can  
tune the PLL parameters to minimize jitter generation or to  
maximize jitter attenuation. Spread spectrum generation is  
supported on one of the PLLs.  
I/O Standards:  
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS  
2 independent adjustable VDDO groups.  
Programmable Slew Rate Control  
Programmable Loop Bandwidth Settings  
Programmable output inversion to reduce bimodal jitter  
Individual output enable/disable  
Spread spectrum generation is supported on one of the  
PLLs. The device is specifically designed to work with  
display applications to ensure that the spread profile  
remains consistent for each HSYNC in order to reduce  
ROW noise. It also may operate in standard spread  
sepctrum mode.  
Power-down/Sleep mode  
– 10μA max in power down mode  
1.8V VDD Core Voltage  
There are total four 8-bit output dividers. The outputs are  
connected to the PLLs via the switch matrix. The switch  
matrix allows the user to route the PLL outputs to any  
output bank. This feature can be used to simplify and  
optimize the board layout. In addition, each output's slew  
rate and enable/disable function can be programmed.  
Available in 20pin 3x3mm QFN packages  
-40 to +85 C Industrial Temp operation  
Target Applications  
Smart Mobile Handset  
Personal Navigation Device (PND)  
Camcorder  
DSC  
Portable Game Console  
Personal Media Player  
®
IDT® VERSACLOCK LOW POWER CLOCK GENERATOR  
1
IDT5P49EE502  
REV D 072610  

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