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542MLF PDF预览

542MLF

更新时间: 2024-02-02 03:47:28
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
6页 171K
描述
CLOCK DIVIDER

542MLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:0.68
系列:542输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.025 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:15 ns传播延迟(tpd):15 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

542MLF 数据手册

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DATASHEET  
CLOCK DIVIDER  
ICS542  
Description  
Features  
The ICS542 is cost effective way to produce a high-quality  
clock output divided from a clock input. The chip accepts a  
clock input up to 156 MHz at 3.3 V and produces a divide by  
2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs  
on the chip, one being a low-skew divide by two of the other.  
8-pin SOIC package, Pb free  
Available in RoHS compliant package  
IDT’s lowest cost clock divider  
Low skew (500 ps) outputs. One is /2 of the other  
Easy to use with other generators and buffers  
Input clock frequency up to 156 MHz  
Output clock duty cycle of 45/55  
Power-down turns off chip  
For instance, if an 100 MHz input clock is used, the ICS542  
can produce low-skew 50 MHz and 25 MHz clocks, or low  
skew 25 MHz and 12.5 MHz clocks. The chip has an  
all-chip power-down mode that stops the outputs low, and  
an OE pin that tri-states the outputs.  
Output Enable  
See the ICS541 and ICS543 for other clock dividers, and  
the ICS501, 502, 511, 512, and 525 for clock multipliers.  
Advanced, low-power CMOS process  
Operating voltage of 3.3 V or 5 V  
Does not degrade phase noise - no PLL  
Available in industrial and commercial temperature  
ranges  
Block Diagram  
VDD  
CLK1  
S1, S0  
Divider  
and  
/2  
Selection  
Circuitry  
CLK2  
Input Clock  
OE (both outputs)  
GND  
IDT™ / ICS™ CLOCK DIVIDER  
1
ICS542  
REV J 051310  

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