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23S05E-1HDCI PDF预览

23S05E-1HDCI

更新时间: 2024-01-16 05:38:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
8页 65K
描述
PLL Based Clock Driver, 23S Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8

23S05E-1HDCI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.53
Is Samacsys:N系列:23S
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3 V传播延迟(tpd):0.35 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
最小 fmax:200 MHzBase Number Matches:1

23S05E-1HDCI 数据手册

 浏览型号23S05E-1HDCI的Datasheet PDF文件第2页浏览型号23S05E-1HDCI的Datasheet PDF文件第3页浏览型号23S05E-1HDCI的Datasheet PDF文件第4页浏览型号23S05E-1HDCI的Datasheet PDF文件第5页浏览型号23S05E-1HDCI的Datasheet PDF文件第6页浏览型号23S05E-1HDCI的Datasheet PDF文件第7页 
IDT23S05E  
3.3V ZERO DELAY CLOCK  
BUFFER, SPREAD SPECTRUM  
COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 200MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT23S05E is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 200MHz.  
• Output Skew < 250ps  
The IDT23S05E is an 8-pin version of the IDT23S09E. IDT23S05E  
accepts one reference input, and drives out five low skew clocks. The -1H  
version of this device operates up to 200MHz frequency and has a higher  
drive than the -1 device. All parts have on-chip PLLs which lock to an input  
clockontheREFpin. ThePLLfeedbackison-chipandisobtainedfromthe  
CLKOUT pad. In the absence of an input clock, the IDT23S05E enters  
• Low jitter <200 ps cycle-to-cycle  
• IDT23S05E-1 for Standard Drive  
• IDT23S05E-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Spread spectrum compatible  
• Available in SOIC package  
power down. In this mode, the device will draw less than 12µA for  
CommercialTemperaturerangeandlessthan2AforIndustrialtempera-  
ture range, the outputs are tri-stated, and the PLL is not running, resulting  
in a significant reduction of power.  
The IDT23S05E is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2010  
1
c
2006 Integrated Device Technology, Inc.  
DSC - 6398/7  

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