23S05-1DCGI

更新时间： 2024-02-03 03:38:45

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
9页	165K
描述
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

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23S05-1DCGI 数据手册

IDT23S05

3.3VZERODELAYCLOCKBUFFER,SPREADSPECTRUM

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT23S05

3.3V ZERO DELAY CLOCK

BUFFER, SPREAD SPECTRUM

COMPATIBLE

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Output Skew < 250ps

The IDT23S05 is an 8-pin version of the IDT23S09. IDT23S05 accepts

one reference input, and drives out five low skew clocks. The -1H version

ofthisdeviceoperatesupto133MHzfrequencyandhasahigherdrivethan

the -1 device. All parts have on-chip PLLs which lock to an input clock on

theREFpin.ThePLLfeedbackison-chipandisobtainedfromtheCLKOUT

pad. In the absence of an input clock, the IDT23S05 enters power down.

• Low jitter <200 ps cycle-to-cycle

• IDT23S05-1 for Standard Drive

• IDT23S05-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Power down mode

• Spread spectrum compatible

• Available in SOIC package

Inthismode,thedevicewilldrawlessthan12µAforCommercialTempera-

turerangeandlessthan25µAforIndustrialtemperaturerange, theoutputs

aretri-stated, andthePLLisnotrunning, resultinginasignificantreduction

of power.

The IDT23S05 is characterized for both Industrial and Commercial

operation.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLK1

PLL

Control

Logic

REF

CLK2

CLK3

CLK4

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

AUGUST 2010

2010 Integrated Device Technology, Inc.

DSC 6381/7

12 3 4 5 6 7...9

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