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2308-5HPGG PDF预览

2308-5HPGG

更新时间: 2024-02-15 15:43:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 165K
描述
3.3V ZERO DELAY CLOCK MULTIPLIER

2308-5HPGG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.02
Is Samacsys:N系列:2308
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e3逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30最小 fmax:133.3 MHz
Base Number Matches:1

2308-5HPGG 数据手册

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3.3V ZERO DELAY  
CLOCK MULTIPLIER  
IDT2308  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution for Applications ranging  
from 10MHz to 133MHz operating frequency  
• Distributes one clock input to two banks of four outputs  
• Separate output enable for each output bank  
• External feedback (FBK) pin is used to synchronize the outputs  
to the clock input  
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is  
designedtoaddresshigh-speedclockdistributionandmultiplicationapplica-  
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming  
clockandtheoutputclock, operablewithintherangeof10to133MHz.  
TheIDT2308hastwobanksoffouroutputseachthatarecontrolledviatwo  
selectaddresses.Byproperselectionofinputaddresses,bothbankscanbe  
put in tri-state mode. In test mode, the PLL is turned off, and the input clock  
directlydrivestheoutputsforsystemtestingpurposes. Intheabsenceofan  
inputclock,theIDT2308enterspowerdown,andtheoutputsaretri-stated.In  
thismode, thedevicewilldrawlessthan25μA.  
• Output Skew <200 ps  
• Low jitter <200 ps cycle-to-cycle  
• 1x, 2x, 4x output options (see table):  
– IDT2308-1 1x  
– IDT2308-2 1x, 2x  
– IDT2308-3 2x, 4x  
– IDT2308-4 2x  
The IDT2308 is available in six unique configurations for both pre-  
scaling and multiplication of the Input REF Clock. (See available options  
table.)  
– IDT2308-1H, -2H, and -5H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser  
tocontrolthedelaybetweentheinputclockandtheoutputs.  
TheIDT2308ischaracterizedforbothIndustrialandCommercialoperation.  
• Available in SOIC and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
(-3, -4)  
16  
2
FBK  
REF  
2
CLKA1  
PLL  
1
2
(-5)  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
9
S2  
S1  
Control  
Logic  
2
(-2, -3)  
6
CLKB1  
CLKB2  
CLKB3  
CLKB4  
7
10  
11  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2010  
1
c
2010 Integrated Device Technology, Inc.  
DSC 5173/12  

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