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2305B-1PGG PDF预览

2305B-1PGG

更新时间: 2024-01-20 05:13:49
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
10页 156K
描述
3.3V ZERO DELAY CLOCK BUFFER

2305B-1PGG 数据手册

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IDT2305B  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts  
one reference input, and drives out five low skew clocks. The -1H version  
of this device operates, up to 133MHz frequency and has a higher drive  
thanthe-1device. Allpartshaveon-chipPLLswhichlocktoaninputclock  
on the REF pin. The PLL feedback is on-chip and is obtained from the  
CLKOUTpad.Intheabsenceofaninputclock,theIDT2305Benterspower  
down. In this mode, the device will draw less than 25µA, the outputs are  
tri-stated, and the PLL is not running, resulting in a significant reduction of  
power.  
• Low jitter <175 ps cycle-to-cycle  
• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)  
• IDT2305B-1 for Standard Drive  
• IDT2305B-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC and TSSOP packages  
The IDT2305B is characterized for both Industrial and Commercial  
operation.  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2007 Integrated Device Technology, Inc.  
DSC 6994/5  

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