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2305B-1DC8 PDF预览

2305B-1DC8

更新时间: 2024-01-11 14:37:10
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 151K
描述
PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8

2305B-1DC8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.63
系列:2305输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.72 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:3.9 mm最小 fmax:133 MHz
Base Number Matches:1

2305B-1DC8 数据手册

 浏览型号2305B-1DC8的Datasheet PDF文件第2页浏览型号2305B-1DC8的Datasheet PDF文件第3页浏览型号2305B-1DC8的Datasheet PDF文件第4页浏览型号2305B-1DC8的Datasheet PDF文件第5页浏览型号2305B-1DC8的Datasheet PDF文件第6页浏览型号2305B-1DC8的Datasheet PDF文件第7页 
IDT2305B  
ADVANCE  
INFORMATION  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
Distributes one clock input to one bank of five outputs  
Zero Input-Output Delay  
The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddress high-speedclockdistributionapplications.The zero  
delayis achieved byaligningthe phase betweenthe incomingclockand  
the outputclock, operable withinthe range of10to133MHz.  
• Output Skew < 250ps  
The IDT2305Bis an8-pinversionofthe IDT2309B.IDT2305Baccepts  
one reference input,anddrives outfive lowskewclocks.The -1Hversion  
of this device operates, up to 133MHz frequency and has a higher drive  
thanthe-1device.Allparts haveon-chipPLLs whichlocktoaninputclock  
on the REF pin. The PLL feedback is on-chip and is obtained from the  
CLKOUTpad.Intheabsenceofaninputclock,theIDT2305Benterspower  
Low jitter <200 ps cycle-to-cycle  
IDT2305B-1 for Standard Drive  
IDT2305B-1H for High Drive  
No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
Available in SOIC package  
down. In this mode, the device will draw less than 25µA, the outputs are  
tri-stated,andthe PLLis notrunning,resultingina significantreductionof  
power.  
The IDT2305B is characterized for both Industrial and Commercial  
operation.  
NOTE: For new designs, refer to AN-233.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2005  
1
c
2005 Integrated Device Technology, Inc.  
DSC 6994/-  

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