Integrated
Circuit
Systems,Inc.
ICS162835
Advance Information
18-Bit 3.3V Registered Buffer
Recommended Applications:
• PC133 Registered Memory Module
Pin Configurations
• PC motherboards
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Y1
GND
Y2
Y3
VDD
Y4
Y5
Y6
GND
Y7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
NC
A1
GND
A2
A3
VDD
A4
A5
A6
GND
A7
• Servers and workstations
• Provides complete PC133 DIMM solution with
ICS2509, ICS2510 PLL.
Product Features:
• Meets JESD 82-2 specification
• Internal series resistors to reduce switching noise
• ±12 mA device capability
Y8
Y9
A8
A9
• Low voltage operation
- VDD = 3.3 ± 0.3V
Y10
Y11
Y12
GND
Y13
Y14
Y15
VDD
Y16
Y17
GND
Y18
OE#
LE
A10
A11
A12
GND
A13
A14
A15
VDD
A16
A17
GND
A18
CLK
GND
• 0.50 mm pitch, 56-Pin TSSOP package
Function Table1
Inputs
Outputs
OE#
H
L
LE
X
H
H
L
CLK
X
Ax
X
L
Yx
Z
X
L
L
X
H
L
H
L
L
↑
L
L
↑
H
X
X
H
(2)
L
L
H
L
Y0
(3)
L
L
Y0
56-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
Notes:
1.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
Pin Description
2.
3.
Output level before the indicated steady-state
input conditions were established, provided that
CLK is HIGH before LE went LOW.
Pin Names Description
OE#
CLK
LE
Output Enable Input (Active Low)
Output level before the indicated steady-state
input conditions were established.
Clock Input
Block Diagram
Latch Enable Input
Data Input
OE#
Ax
Yx
Data Outputs
Supply Voltage
Ground
CLK
LE
VDD
GND
Y1
1D
C1
A1
CK
To 17 Other Channels
0713—09/23/02
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.