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1562BM-001T PDF预览

1562BM-001T

更新时间: 2024-02-28 21:26:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
21页 515K
描述
Video Clock Generator, 260MHz, CMOS, PDSO16, 0.150 INCH, SKINNY, SOIC-16

1562BM-001T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SKINNY, SOIC-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.77JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.906 mm
湿度敏感等级:1端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:260 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225电源:5 V
主时钟/晶体标称频率:20 MHz认证状态:Not Qualified
子类别:Clock Generators最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9116 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

1562BM-001T 数据手册

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DATA SHEET  
ICS1562B  
User Programmable Differential  
Output Graphics Clock Generator  
Description  
Features  
The ICS1562B is a very high performance monolithic phase-  
locked loop (PLL) frequency synthesizer. Utilizing ICS’s ad-  
vanced CMOS mixed-mode technology, the ICS1562B  
provides a low cost solution for high-end video clock genera-  
tion.  
Two programming options:  
ICS1562B-001 (Parallel Programming)  
ICS1562B-201 (Serial Programming)  
Supports high-resolution graphics - CLK output to  
260 MHz, with 400 MHz options available  
Eliminates need for multiple ECL output crystal oscillators  
Fully programmable synthesizer capability - not just a  
clock multiplier  
The ICS1562B hasdifferentialvideoclockoutputs (CLK+and  
CLK-) that are compatible with industry standard video DAC.  
Another clock output, LOAD, is provided whose frequency is  
derived from the main clock by a programmable divider. An  
additional clock output is available, LD/N2, which is derived  
from the LOAD frequency and whose modulus may also be  
programmed.  
Circuitry included for reset of Brooktree RAMDAC pipe-  
line delay  
VRAM shift clock generation capability  
(-201 option only)  
External feedback loop capability (-201 option only)  
Operating frequencies arefully programmable with direct con-  
trol provided for reference divider, prescaler, feedback divider  
and post-scaler.  
Compact - 16-pin 0.150” skinny SOIC package  
Fully backward compatible to ICS1562  
Reset of the pipeline delay on Brooktree RAMDAC s may  
be performed under register control. Outputs may also be set  
to desired states to facilitate circuit board testing.  
ICS1562B - 001 Pinout  
Simplified Block Diagram - ICS1562B  
LOOP  
FILTER  
AD0  
XTAL1  
XTAL2  
STROBE  
VSS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
AD1  
XTAL1  
XTAL2  
AD2  
CRYSTAL  
OSCILLATOR  
PHASE-  
/ R  
CHARGE  
PUMP  
VCO  
FREQUENCY  
DETECTOR  
AD3  
VDD  
VDDO  
IPRG  
CLK+  
CLK-  
PRESCALER  
EXTFBK  
BLANK  
VSS  
(-201 only)  
MUX  
/ A  
/ M  
LOAD  
LD/N2  
FEEDBACK DIVIDER  
PROGRAMMING  
INTERFACE  
16-Pin SOIC  
MUX  
CLK+  
/ 2  
/ 4  
DIFF.  
OUTPUT  
CLK−  
ICS1562B - 201 Pinout  
EXTFBK  
XTAL1  
XTAL2  
DATCLK  
VSS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
DATA  
HOLD  
BLANK  
VDD  
/ N1  
MUX  
DRIVER  
LOAD  
LD/N2  
/ N2  
VDDO  
IPRG  
CLK+  
CLK-  
DRIVER  
VSS  
LOAD  
LD/N2  
Figure 1  
16-Pin SOIC  
IDT™ /ICSUserProgrammable Differential Output Graphics Clock Generator  
ICS1562B  
1

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