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1524AMT PDF预览

1524AMT

更新时间: 2024-02-12 08:13:09
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
24页 354K
描述
Clock Generator, 250MHz, CMOS, PDSO24, 0.300INCH, SOIC-24

1524AMT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300INCH, SOIC-24
针数:24Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.3416 mm
湿度敏感等级:1端子数量:24
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:250 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225电源:3.3 V
主时钟/晶体标称频率:100 MHz认证状态:Not Qualified
座面最大高度:2.8194 mm子类别:Clock Generators
最大压摆率:25 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:7.5184 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

1524AMT 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS1524A  
Dual Output Phase Controlled SSTL_3/PECL Clock Generator  
General Description  
Features  
Wide input frequency range  
The ICS1524A is a low-cost, very high-performance  
frequency generator and phase controlled clock synthe-  
sizer. It is perfectly suited to phase controlled clock  
synthesis and distribution as well as line-locked and  
genlocked applications.  
• 8 kHz to 100 MHz  
250 MHz balanced PECL differential outputs  
150 MHz single-ended SSTL_3 clock outputs  
Dynamic Phase Adjust (DPA) for DPACLK  
outputs  
The ICS1524A offers two channels of clock phase con-  
trolled outputs; CLK and DPACLK. These two output  
channels have both 250 MHz PECL differential and 150  
MHz SSTL_3 single-ended output pins. The CLK output  
channel has a fixed phase relationship to the PLL’s input  
and the DPACLK uses the Dynamic Phase Adjust cir-  
cuitry to allow control of the clock phase relative to input  
signal.  
• Software controlled phase adjustment  
• 360o Adjustment down to 1/64 clock  
increments  
External or internal loop filter selection  
Uses 3.3 VDC Inputs are 5 volt tolerant.  
I2C-bus serial interface runs at either low speed  
(100 kHz) or high speed (400 kHz).  
Optionally, the CLK outputs can operate at half the clock  
rate and phase aligned with the DPACLK channel, en-  
abling deMUXing of multiplexed analog-to-digital  
converters. The FUNC pin provides either the regener-  
ated input from the phase-locked loop (PLL) divider  
chain output or a re-synchronized and sharpened input  
HSYNC.  
Hardware and Software PLL Lock detection  
Applications  
Generic Frequency Synthesis  
LCD Monitors and Projectors  
Genlocking Multiple Video Systems  
The advanced PLL uses either its internal program-  
mable feedback divider or an external divider and is  
programmed by a standard I2C-bus™ serial interface.  
Block Diagram  
Pin Configuration  
Loop  
Filter  
IREF  
CLK+  
CLK–  
DPACLK+ (PECL)  
DPACLK– (PECL)  
VSSQ  
VDDQ  
DPACLK (SSTL)  
CLK  
FUNC  
VDDD  
VSSD  
SDA  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
(PECL)  
(PECL)  
CLK  
SCL  
CLK+/-  
HSYNC  
PDEN  
EXTFB  
HSYNC  
EXTFIL  
XFILRET  
VDDA  
VSSA  
DPACLK  
DPACLK+/-  
FUNC  
OSC  
I2C  
(SSTL)  
(SSTL)  
10  
11  
12  
LOCK/REF (SSTL)  
2
I CADR  
OSC  
24 Pin 300-mil SOIC  
I2C-bus is a trademark of Philips Corporation.  
ICS reserves the right to make changes in the device data identified in this  
publication without further notice. ICS advises its customers to obtain the  
latest version of all device data to verify that any information being relied  
upon by the customer is current and accurate.  
ICS1524A Rev D 12/23/2005  

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