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1523MT PDF预览

1523MT

更新时间: 2024-02-24 14:36:37
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
21页 460K
描述
Video Clock Generator, 250MHz, CMOS, PDSO24, 0.300 INCH, SOIC-24

1523MT 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, SOIC-24
针数:24Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.74Is Samacsys:N
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
湿度敏感等级:1端子数量:24
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:250 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE主时钟/晶体标称频率:100 MHz
认证状态:Not Qualified座面最大高度:2.8194 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5184 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

1523MT 数据手册

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ICS1523  
2
Video Clock Synthesizer with I C Programmable Delay  
Features  
General Description  
• Low Jitter  
• Wide input frequency range  
The ICS1523 is a low-cost, high-performance  
frequency generator. It is well suited to general  
purpose phase controlled clock synthesis as well as  
line-locked and genlocked high-resolution video  
applications. Using IDT’s advanced low-voltage  
CMOS mixed-mode technology, the ICS1523 is an  
effective phase controlled clock synthesizer and also  
supports video projectors and displays at resolutions  
from VGA to beyond UXGA.  
• 15.734 kHz to 100 MHz  
• PECL differential outputs  
• Up to 250 MHz  
• SSTL_3 Single-ended clock outputs  
• Up to 150 MHz  
• Dynamic Phase Adjust (DPA) for all outputs  
2
The ICS1523 offers clock outputs in both differential  
(to 250 MHz) and single-ended (to 150 MHz) formats.  
Dynamic Phase Adjust (DPA) allows I C™ control of  
• I C controlled phase adjustment  
• Full clock cycle down to 1/64 of a clock  
• Double-buffered control registers  
• External or internal loop filter selection  
• COAST input can disable charge pump  
• 3.3 VDD  
2
the output clock’s phase relative to the input sync  
signal. A second, half speed set of outputs that can be  
separately enabled allows such applications as  
clocking analog-to-digital converters. The FUNC pin  
provides either the regenerated input from the  
phase-locked loop (PLL) divider chain output, or the  
input HSYNC after being sharpened by the Schmitt  
trigger. Both signals are then delayed by the DPA.  
• 5 volt Tolerant Inputs  
2
• Industry Standard I C-bus programming interface  
2
• PLL Lock detection via I C or LOCK/REF output pin  
• 24-pin 300-mil SOIC package  
The advanced PLL uses either its internal  
programmable feedback divider or an external divider.  
Either the internal or external loop filters is software  
selectable. The COAST input pin disables the PLL’s  
charge pump, causing the device to idle at the current  
speed for short periods of time, such as vertical  
blanking intervals.  
Applications  
• Frequency synthesis  
• LCD monitors, video projectors and plasma displays  
• Genlocking multiple video subsystems  
The device is programmed by a standard I2C-bus  
serial interface and is available in a 24-pin, wide  
small-outline integrated circuit (SOIC) package.  
Pin Configuration  
ICS1523 Functional Diagram  
External Loop Filter (optional)  
OSC  
HSYNC  
I2C I/F  
24-pin SOIC  
CLK  
CLK/2  
FUNC  
MDS ICS1523 ZB  
1
Revision 051310  
Integrated Device Technology, Inc.Tech Support: www.idt.com/go/clockhelp  

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