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ICS9DB202CGLF PDF预览

ICS9DB202CGLF

更新时间: 2024-11-19 03:33:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管衰减器PC
页数 文件大小 规格书
13页 673K
描述
PCI EXPRESS JITTER ATTENUATOR

ICS9DB202CGLF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
系列:9DB输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:20实输出次数:2
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.11 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

ICS9DB202CGLF 数据手册

 浏览型号ICS9DB202CGLF的Datasheet PDF文件第2页浏览型号ICS9DB202CGLF的Datasheet PDF文件第3页浏览型号ICS9DB202CGLF的Datasheet PDF文件第4页浏览型号ICS9DB202CGLF的Datasheet PDF文件第5页浏览型号ICS9DB202CGLF的Datasheet PDF文件第6页浏览型号ICS9DB202CGLF的Datasheet PDF文件第7页 
PCI EXPRESS JITTER ATTENUATOR  
ICS9DB202  
GENERAL DESCRIPTION  
FEATURES  
The ICS9DB202 is a high perfromance 1-to-2  
Differential-to-HCSL Jitter Attenuator designed for  
use in PCI Express™ systems. In some PCI  
Express™ systems, such as those found in desktop  
PCs, the PCI Express™ clocks are generated from  
Two 0.7V current mode differential HCSL output pairs  
ICS  
HiPerClockS™  
One differential clock input  
CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
a low bandwidth, high phase noise PLL frequency synthesizer.  
In these systems, a jitter-attenuating device may be necessary  
in order to reduce high frequency random and deterministic  
jitter components from the PLL synthesizer and from the system  
board. The ICS9DB202 has two PLL bandwidth modes. In low  
bandwidth mode, the PLL loop bandwidth is 500kHz.This setting  
offers the best jitter attenuation and is still high enough to pass  
a triangular input spread spectrum profile. In high bandwidth  
mode, the PLL bandwidth is at 1MHz and allows the PLL to  
pass more spread spectrum modulation.  
Maximum output frequency: 140MHz  
Input frequency range: 90MHz - 140MHz  
VCO range: 450MHz - 700MHz  
Output skew: 110ps (maximum)  
Cycle-to-cycle jitter: 110ps (maximum)  
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):  
2.42ps (typical)  
3.3V operating supply  
For serdes which have x10 reference multipliers instead of x12.5  
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)  
can be set for 125MHz instead of 100MHz by configuring the  
appropriate frequency select pins (FS0:1).  
0°C to 70°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
IREF  
Current  
Set  
-
+
VDDA  
PLL_BW  
CLK  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
BYPASS  
IREF  
FS1  
VDD  
GND  
PCIEXT1  
PCIEXC1  
VDD  
nCLK  
FS0  
VDD  
1 HiZ  
0 Enabled  
nOE0  
GND  
PCIEXT0  
PCIEXC0  
VDD  
0
1
PCIEXT0  
nPCIEXC0  
nCLK  
CLK  
Loop  
Filter  
Phase  
Detector  
0 ÷4  
1 ÷5  
nOE1  
nOE0  
VCO  
ICS9DB202  
20-Lead TSSOP  
6.50mm x 4.40mm x 0.92  
package body  
FS0  
÷5  
G Package  
Top View  
Internal Feedback  
0
1
PCIEXT1  
nPCIEXC1  
0 ÷5  
1 ÷4  
ICS9DB202  
20-Lead, 209-MIL SSOP  
5.30mm x 7.20mm x 1.75mm  
body package  
F Package  
Top View  
FS1  
BYPASS  
nOE1  
1 HiZ  
0 Enabled  
IDT/ ICSPCI EXPRESS JITTER ATTENUATOR  
1
ICS9DB202CG REV B JULY 14, 2006  

ICS9DB202CGLF 替代型号

型号 品牌 替代类型 描述 数据表
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