Datasheet > ICS954204GT

ICS954204GT

更新时间： 2024-11-12 10:20:35

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
16页	199K
描述
Clock Generator, PDSO56

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数据手册

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ICS954204GT 数据手册

Integrated

Circuit

ICS954204

Systems, Inc.

Programmable Timing Control Hub™ for Mobile P4™ Systems

Recommended Application:

CK410M Compliant Main Clock with Integrated LCD Spread

Spectrum Clock.

•

PCI outputs cycle-cycle jitter < 500ps

+/- 300ppm frequency accuracy on CPU & SRC clocks

+/- 100ppm frequency accuracy on USB clocks

Features/Benefits:

Output Features:

•

Supports tight ppm accuracy clocks for Serial-ATA and

SRC

•

2 - 0.7V current-mode differential CPU pairs

5 - 0.7V current-mode differential SRC pair for SATA and

PCI-E

•

Supports programmable spread percentage and

frequency

•

1 - 0.7V current-mode differential CPU/SRC selectable

pair

•

Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

•

4 - PCI (33MHz)

2 - PCICLK_F, (33MHz) free-running

1 - USB, 48MHz

1 - DOT, 96MHz, 0.7V current differential pair

1 - REF, 14.318MHz

1 - 0.7V current-mode differential LCD/SRC selectable

pair.

Supports undriven differential CPU, SRC pair in PD#

for power management.

CLKREQ pins to support SRC power management.

Key Specifications:

•

CPU outputs cycle-cycle jitter < 85ps

SRC outputs cycle-cycle jitter < 125ps

Pin Configuration

Functionality

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

VDDPCI 1

56 PCICLK2

FS_C FS_B FS_A

GND 2

PCICLK3 3

PCICLK4 4

PCICLK5 5

GND 6

55 PCI/SRC_STOP#

54 CPU_STOP#

53 FS_LC/TEST_SEL

52 REFOUT

51 GND

50 X1

49 X2

48 VDDREF

47 SDATA

46 SCLK

266.67 100.00 33.33

133.33 100.00 33.33

200.00 100.00 33.33

166.67 100.00 33.33

333.33 100.00 33.33

100.00 100.00 33.33

400.00 100.00 33.33

200.00 100.00 33.33

14.318

48.00

96.00

VDDPCI 7

ITP_EN/PCICLK_F0 8

*SELSRC_LCDCLK#/PCICLK_F1 9

Vtt_PwrGd#/PD 10

VDD48 11

FS_LA/USB_48MHz 12

45 GND

FS_C is a three-level input. Please see V_{IL_FS}and V_{IH_FS}specifications in the

Input/Supply/Common Output Parameters Table for correct values. Also refer

to the Test Clarification Table.

GND 13

DOTT_96MHz 14

DOTC_96MHz 15

44 CPUCLKT0

43 CPUCLKC0

42 VDDCPU

41 CPUCLKT1

40 CPUCLKC1

39 IREF

FS_LB/TEST_MODE 16

FS_B and FS_A are low-threshold inputs. Please see the V_{IL_FS}and V_{IH_FS}

specifications in the Input/Supply/Common Output Parameters Table for

correct values.

LCDCLK_SST/SRCCLKT0 17

LCDCLK_SSC/SRCCLKC0 18

SRCCLKT1 19

38 GNDA

SRCCLKC1 20

37 VDDA

VDDSRC 21

SRCCLKT2 22

SRCCLKC2 23

36 CPUCLKT2_ITP/SRCCLKT7

35 CPUCLKC2_ITP/SRCCLKC7

34 VDDSRC

SRCCLKT3 24

33 CLKREQA#*

SRCCLKC3 25

32 CLKREQB#*

SRCCLKT4_SATA 26

SRCCLKC4_SATA 27

VDDSRC 28

31 SRCCLKT5

30 SRCCLKC5

29 GND

56-pin TSSOP

*100Kohm Pull-Up Resistor

0933D—03/16/05

12 3 4 5 6 7...16

中文翻译

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与ICS954204GT相关器件

型号	品牌	获取价格	描述	数据表
ICS954204YGLFT	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, LEAD FREE, MO-
ICS954204YGT	IDT	获取价格	Processor Specific Clock Generator, 400MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-
ICS95420YGLFT	ICSI	获取价格	Programmable Timing Control HubTM for Mobile P4TM Systems
ICS95420YGLNT	ICSI	获取价格	Programmable Timing Control HubTM for Mobile P4TM Systems
ICS954310BGLF	IDT	获取价格	PC MAIN CLOCK
ICS95V157AGIT	IDT	获取价格	PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240
ICS95V157AGI-T	IDT	获取价格	95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, 0.240
ICS95V157AGLF	IDT	获取价格	PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240
ICS95V157AGLFT	IDT	获取价格	PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240
ICS95V157AGT	IDT	获取价格	PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240

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