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ICS951901FLF-T PDF预览

ICS951901FLF-T

更新时间: 2024-11-21 20:10:19
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
19页 180K
描述
Clock Generator, PDSO48

ICS951901FLF-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.84
JESD-30 代码:R-PDSO-G48端子数量:48
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH电源:2.5,3.3 V
认证状态:Not Qualified子类别:Clock Generators
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

ICS951901FLF-T 数据手册

 浏览型号ICS951901FLF-T的Datasheet PDF文件第2页浏览型号ICS951901FLF-T的Datasheet PDF文件第3页浏览型号ICS951901FLF-T的Datasheet PDF文件第4页浏览型号ICS951901FLF-T的Datasheet PDF文件第5页浏览型号ICS951901FLF-T的Datasheet PDF文件第6页浏览型号ICS951901FLF-T的Datasheet PDF文件第7页 
ICS951901  
Integrated  
Circuit  
Systems, Inc.  
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor  
Recommended Application:  
Pin Configuration  
Single chip clock solution for IA platform.  
VDDA  
(AGPSEL)REF0  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDL  
1
Output Features:  
*
CPUCLK0  
CPUCLK1  
CPUCLK2  
GND  
VDDSDR  
SDRAM0  
SDRAM1  
SDRAM2  
GND  
SDRAM3  
SDRAM4  
SDRAM5  
VDDSDR  
SDRAM6  
SDRAM7  
GND  
SDRAM8/PD#  
SDRAM9/SDRAM_STOP#  
GND  
SDRAM10/PCI_STOP#  
SDRAM11/CPU_STOP#  
SDRAM12  
VDDSDR  
1
*(FS3)REF1  
3 - CPU @ 2.5V  
GND  
X1  
X2  
13 - SDRAM @ 3.3V  
6 - PCI @3.3V,  
VDDPCI  
*(FS1)PCICLK_F  
*(FS2)PCICLK0  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK4  
GND  
2 - AGP @ 3.3V  
1 - 48MHz, @3.3V fixed.  
1 - 24/48MHz, @3.3V selectable by I2C  
(Default is 24MHz)  
2 - REF @3.3V, 14.318MHz.  
VDDAGP  
AGPCLK0  
AGPCLK1  
GND  
Features:  
Programmable ouput frequency.  
Programmable ouput rise/fall time.  
Programmable SDRAM and CPU skew.  
Spread spectrum for EMI control typically  
by 7dB to 8dB,  
GND  
*(FS0)48MHz  
*(MODE)24_48MHz  
VDD48  
SDATA  
SCLK  
with programmable spread percentage.  
Watchdog timer technology to reset system  
if over-clocking causes malfunction.  
Uses external 14.318MHz crystal.  
FS pins for frequency select  
48-Pin 300mil SSOP  
* These inputs have a 120K pull down to GND.  
1 These are double strength.  
Skew Specifications:  
CPU - CPU: < 175ps  
SDRAM - SDRAM < 250ps (except SDRAM12)  
PCI - PCI: < 500ps  
CPU (early) - PCI: 1-4ns (typ. 2ns)  
Block Diagram  
Functionality  
SDRAM  
MHz  
FS3  
Bit7  
FS2  
Bit6  
FS1  
Bit5  
FS0  
Bit4 MHz  
CPU  
PCI  
MHz  
AGP1  
SEL=1  
AGP0  
SEL=0  
PLL2  
48MHz  
Bit2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67  
66.67  
66.67  
75.00  
83.31  
90.00  
95.00  
100.00  
66.67  
100.00  
133.34  
75.00  
83.31  
90.00  
95.00  
66.67  
33.33  
33.33  
33.33  
37.50  
33.32  
30.00  
31.67  
33.33  
33.33  
33.33  
35.00  
33.60  
35.40  
31.02  
33.33  
33.33  
66.67  
66.67  
66.67  
75.00  
66.64  
60.00  
63.33  
66.67  
66.67  
66.67  
70.00  
67.20  
70.80  
62.05  
66.67  
66.67  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
24_48MHz  
/ 2  
X1  
X2  
XTAL  
OSC  
REF(1:0)  
2
3
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
Stop  
CPUCLK (2:0)  
SDRAM (12:0)  
SDRAM  
DIVDER  
100.00 100.00  
100.00 133.34  
105.00 105.00  
112.00 112.00  
117.99 117.99  
124.09 124.09  
133.34 100.00  
133.34 133.34  
Stop  
Stop  
13  
5
SDATA  
SCLK  
Control  
Logic  
PCI  
DIVDER  
PCICLK (4:0)  
PCICLK_F  
AGP (1:0)  
FS(3:0)  
PD#  
AGP  
DIVDER  
PCI_STOP#  
CPU_STOP#  
SDRAM_STOP#  
MODE  
2
Config.  
Reg.  
AGP_SEL  
0670B—07/15/04  

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