Datasheet > ICS93V855YGT

ICS93V855YGT

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
9页	66K
描述
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28

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ICS93V855YGT 数据手册

ICS93V855

Integrated

Circuit

Systems, Inc.

DDR Phase Lock Loop Clock Driver

Recommended Application:

Pin Configuration

DDR Clock Driver

GND

DDRC0

DDRT0

VDD2.5

CLK_INT

CLK_INC

AVDD2.5

AGND

28 DDRC4

27 DDRT4

26 VDD2.5

25 GND

24 FB_OUTC

23 FB_OUTT

22 VDD2.5

21 FB_INT

20 FB_INC

19 GND

Product Description/Features:

•

Low skew, low jitter PLL clock driver

External feedback pins for input to output

synchronization

•

Spread Spectrum tolerant inputs

With bypass mode mux

Operating frequency 60 to 170 MHz

GND

DDRC1 10

DDRT1 11

VDD2.5 12

DDRT2 13

DDRC2 14

18 VDD2.5

17 DDRT3

16 DDRC3

15 GND

Switching Characteristics:

•

CYCLE - CYCLE jitter:<75ps

OUTPUT - OUTPUT skew: <60ps

•

Output Rise and Fall Time: 650ps - 950ps

28-Pin 4.4mm TSSOP

Block Diagram

Functionality

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLK_INC DDRT DDRC FB_OUTT FB_OUTC

GND

Bypassed/Off

FB_OUTT

FB_OUTC

2.5V

(nom)

DDRT0

DDRC0

Off

2.5V

(nom)

DDRT1

DDRC1

2.5V

(nom)

<20 MHz <20 MHz Hi-Z

Hi-Z

DDRT2

DDRC2

Control

Logic

DDRT3

DDRC3

DDRT4

DDRC4

FB_INT

FB_INC

PLL

CLK_INC

CLK_INT

AVDD2.5

0497B—06/01/04

12 3 4 5 6 7...9

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