Integrated
Circuit
ICS932S422C
Systems, Inc.
PCIe Gen 2 main Clock for Intel-based Servers
Recommended Application:
Features/Benefits:
PCIe Gen 2 & FBD compliant CK410B/CK410B+ clock for
Intel-based servers
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
•
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
Output Features:
•
•
•
•
•
•
5 - 0.7V current-mode differential CPU pairs
4 - 0.7V current-mode differential SRC pair
4 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - 48MHz
•
•
•
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
Compliant with PCIe Gen II phase noise specifications
2 - REF, 14.318MHz
Key Specifications:
•
•
•
•
•
•
CPU cycle-cycle jitter: < 50ps
SRC cycle-cycle jitter: < 125ps
PCI cycle-cycle jitter: < 500ps
CPU output skew: < 100ps
SRC output skew: < 250ps
300ppm frequency accuracy on all outputs except
48MHz
•
100ppm frequency accuracy on 48MHz
Functionality
Pin Configuration
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
VDDPCI 1
GNDPCI 2
PCICLK0 3
PCICLK1 4
PCICLK2 5
PCICLK3 6
GNDPCI 7
VDDPCI 8
PCICLK_F0 9
PCICLK_F1 10
PCICLK_F2 11
VDD48 12
48MHz 13
GND48 14
VDDSRC 15
NC 16
56 FSLC/TEST_SEL
55 REF0
54 REF1
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 FSLA
47 VDDCPU
46 CPUCLKT0
45 CPUCLKC0
44 VDDCPU
43 CPUCLKT1
42 CPUCLKC1
41 GNDCPU
40 CPUCLKT2
39 CPUCLKC2
38 VDDCPU
37 CPUCLKT3
36 CPUCLKC3
35 VDDA
FSLC1 FSLB1 FSLA2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.67 100.00
133.33 100.00
200.00 100.00
166.67 100.00
333.33 100.00
100.00 100.00
400.00 100.00
33.33
33.33
33.33
33.33
33.33
33.33
33.33
Reserved
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48.000
48.000
48.000
48.000
48.000
48.000
48.000
1. FSLB and FSLC are three-level inputs. Please see VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values. Also refer to the Test Clarification Table.
2.FSLA is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Vtt_PwrGd#/PD 17
SRCCLKC1 18
SRCCLKT1 19
GNDSRC 20
SRCCLKT2 21
SRCCLKC2 22
SRCCLKC3 23
SRCCLKT3 24
VDDSRC 25
SRCCLKT4 26
SRCCLKC4 27
VDDSRC 28
34 GNDA
33 IREF
32 CPUCLKT4
31 CPUCLKC4
30 SDATA
29 SCLK
56-pin SSOP & TSSOP
1412A—12/10/07