Datasheet > ICS9250BF-12LFT

ICS9250BF-12LFT

更新时间： 2024-09-25 20:59:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
12页	397K
描述
Clock Generator

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中文翻译

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技术参数
数据手册

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ICS9250BF-12LFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.81
JESD-609代码：	e3	湿度敏感等级：	1
端子面层：	Matte Tin (Sn) - annealed	Base Number Matches：	1

ICS9250BF-12LFT 数据手册

Integrated

Circuit

Systems, Inc.

ICS9250-12

Frequency Timing Generator for PENTIUM II/III Systems

General Description

Features

Generates the following system clocks:

The ICS9250-12 is a main clock synthesizer chip for

Pentium II based systems using Rambus Interface DRAMs.

This chip provides all the clocks required for such a system

when used with a Direct Rambus Clock Generator (DRCG)

chip such as the ICS9212-01, 02, 03 and a PCI buffer 9112-17.

- 4CPUclocks(2.5V,100/133MHz)

- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)

- 2CPU/2clocks(2.5V, 50/66MHz)

-3IOAPICclocks(2.5V,16.67MHz)

-4Fixedfrequency66MHzclocks(3.3V, 66MHz)

-2REFclocks(3.3V,14.318MHz)

Spread Spectrum may be enabled by driving the SPREAD#

pin active. Spread spectrum typically reduces system EMI

by 8dB to 10dB. This simplifies EMI qualification without

resorting to board design iterations or costly shielding. The

ICS9250-12 employs a proprietary closed loop design,

which tightly controls the percentage of spreading over

process and temperature variations.

-1USBclock(3.3V,48MHz)

Efficient power management through PD#, CPU_STOP#

andPCI_STOP#.

0.5% typical down spread modulation on CPU, PCI,

IOAPIC, 3V66 and CPU/2 output clocks.

The CPU/2 clocks are inputs to the DRCG.

Usesexternal14.318MHzcrystal.

Key Specification:

CPU Output Jitter: 150ps

IOAPIC Output Jitter: 250ps

CPU/2, 3V66, PCIOutputJitter:250ps

CPU(0:3)CPU/2OutputSkew:<175ps

PCI_F, PCI1:7OutputSkew:<500ps

3V66(0:3)OutputSkew<250ps

Pin Configuration

IOAPIC(0:2)OutputSkew<250ps

CPU to 3V66 (0:3) Output Offset: 0.0 - 1.5ns (CPU leads)

CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)

CPU toAPIC Output Offset 1.5 - 4.0ns (CPU leads)

Block Diagram

56-pin SSOP

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

9250-12 Rev B 2/23/00

information being relied upon by the customer is current and accurate.

12 3 4 5 6 7...12

中文翻译

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与ICS9250BF-12LFT相关器件

型号	品牌	获取价格	描述	数据表
ICS9250BF-16	IDT	获取价格	Processor Specific Clock Generator, 150MHz, PDSO56, 0.300 INCH, SSOP-56
ICS9250BF-16LF-T	IDT	获取价格	Processor Specific Clock Generator, 150MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
ICS9250BF-27	IDT	获取价格	Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, MO-118,
ICS9250BF-27LFT	IDT	获取价格	Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, GREEN, M
ICS9250BF-28LF-T	IDT	获取价格	Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
ICS9250CF-10LF	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
ICS9250CF-10LFT	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
ICS9250CF-10T	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO56, 0.300 INCH, SSOP-56
ICS9250F-16T	IDT	获取价格	Clock Generator
ICS9250F-18	IDT	获取价格	Clock Generator, PDSO56, SSOP-56

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