ICS9250-38
Integrated
Circuit
Systems, Inc.
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK 408 clock for Almador-M mobile chipset with Tualatin
PIII processor.
Pin Configuration
Output Features:
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
FS1
FS0
•
•
•
•
•
•
•
•
•
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB
48MHz_DOT
VDD48
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
1 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
•
1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
66MHz_OUT0/3V66_2
66MHz_OUT1/3V66_3
66MHz_OUT2/3V66_4
66MHz_IN/3V66_5
*PD#
GND
3V66_1/VCH_CLK
PCI_STOP#*
3V66_0
VDD3V66
GND
Features:
•
Almador Chipset has a DLL driving the clock buffer
path for the 3 buffer path 66.6 MHz outputs,
66Buf(0:2).
VDDA
GND
Vtt_PWRGD#
SCLK
SDATA
Almador board level designs MUST use pin 22,
66Buf_1, as the feedback connection from the
clock buffer path to the Almador (GMCH)
chipset.
56-Pin 300mil SSOP/TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
•
•
Supports spread spectrum modulation,
down spread 0 to -0.5%.
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
66MHz Output Jitter (Buffered Mode Only) <100ps Functionality
CPU Output Skew <100ps
Block Diagram
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
CPU
(MHz)
3V66
(MHz)
FS2
FS1
FS0
PLL2
48MHz_USB
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66.66
100.00
200.00
133.33
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
Tristate
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
48MHz_DOT
X1
X2
XTAL
OSC
3V66_1/VCH_CLK
0
REF
66MHz_IN
0
PLL1
Spread
Spectrum
CPUCLKT (2:0)
CPUCLKC (2:0)
1
66MHz_IN 66MHz_IN/2
66MHz_IN 66MHz_IN/2
66MHz_IN 66MHz_IN/2
66MHz_IN 66MHz_IN/2
CPU
DIVDER
3
Stop
Stop
3
1
100.00
200.00
133.33
Tristate
PCI
DIVDER
PCICLK (6:0)
1
7
3
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
PCICLK_F (2:0)
1
Control
Logic
66MHz
DIVDER
66MHz_OUT (2:0)
3V66 (5:2,0)
Mid
Mid
Mid
Mid
Tristate
TCLK/4
Tristate
TCLK/8
3
5
3V66
DIVDER
TCLK/2 TCLK/4
Config.
Reg.
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved
Reserved
SDATA
SCLK
I REF
0404B—12/23/02