DATASHEET
Frequency Generator and Integrated Buffers
for Celeron & PII/IIITM
ICS9250-27
Pin Configuration
Recommended Application:
810/810E and 815 type chipset.
*FS2//REF0
VDD
1
2
56
GND
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
3
4
5
6
7
8
9
Output Features:
•
3 CPU (2.5V) (up to 133MHz achievable through I2C)
•
9 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
VDD
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
PD#
SCLK
SDATA
FS1
•
•
•
•
•
7 PCI (3.3 V) @33.3MHz
2 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
Features:
VDD
GND
GND
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
48MHz_0
48MHz_1
VDD
•
•
•
•
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I2C
control.
FS0
56-Pin 300mil SSOP
* This input has a 50KΩ pull-down to GND.
Block Diagram
Functionality
X1
X2
XTAL
OSC
REF0
FS2
FS1
FS0
Function
PLL1
Spread
Spectrum
X
X
0
0
0
1
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
/2
/3
0
0
1
1
1
1
1
1
0
1
0
1
VDDL
CPU66/100/133 (2:0)
3
3
8
Active CPU = 100MHz
SDRAM = 100MHz
3V66 (2:0)
FS (2:0)
PD#
Control
Logic
Active CPU = 133MHz
SDRAM = 133MHz
SDRAM (7:0)
SDRAM_F
Active CPU = 133MHz
SDRAM = 100MHz
SDATA
SCLK
PCICLK (5:0)
PCICLK_F
/2
6
2
Config
Reg
IOAPIC (1:0)
VDDL
/2
Power Groups
PLL2
48MHz (1:0)
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND = Pin 24 Analog ground for 48MHz PLL
2
IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
0395F—01/25/10
1