Integrated
Circuit
Systems, Inc.
ICS9250-26
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset. Provides three CPU speeds
(66.6, 100, 133MHz) with SDRAM = 133.3MHz.
Pin Configuration
*FS2//REF0
VDD0
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GNDL1
IOAPIC0
IOAPIC1
VDDL1
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL0
GND5
SDRAM0
SDRAM1
VDD5
SDRAM2
SDRAM3
GND5
SDRAM4
SDRAM5
VDD5
SDRAM6
SDRAM7
GND5
SDRAM_F
VDD5
PD#
Output Features:
X1
X2
GND0
GND1
3V66-0
3V66-1
VDD1
3
4
5
6
7
8
9
•
3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz
achievable through I2C)
•
9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz
achievable through I2C)
VDD2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
•
•
•
•
•
8 PCI (3.3 V) @33.3MHz
PCICLK0
PCICLK1
PCICLK2
GND2
PCICLK3
PCICLK4
GND2
PCICLK5
PCICLK6
PCICLK7
VDD2
2 IOAPIC (2.5V) @ 33.3 MHz
2 Hublink clocks (3.3 V) @ 66.6 MHz
2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
•
Supports spread spectrum modulation ,
down spread 0 to -0.5% and
0.25% center spread.
VDD3
GND3
GND4
•
•
•
•
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I2C
control.
48MHz_0
48MHz_1
VDD4
SCLK
SDATA
FS1
FS0
56-Pin 300mil SSOP
* This input has a 120KΩ pull-down to GND.
Block Diagram
Functionality
FS2
FS1
FS0
Function
X
X
0
0
0
1
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
0
0
1
1
1
1
0
1
1
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 100MHz
(Special Condition)
Active CPU = 133MHz
SDRAM = 133MHz
1
1
0
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-26 Rev B 01/19/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.