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ICS9250-16 PDF预览

ICS9250-16

更新时间: 2024-09-24 22:55:27
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
17页 540K
描述
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩

ICS9250-16 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9250-16  
Frequency Generator & Integrated Buffers for Celeron & PII/III™  
Recommended Application:  
Pin Configuration  
810/810E type chipsetꢀ  
Output Features:  
*FS2//REF0  
VDD0  
1
2
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GNDL1  
IOAPIC0  
IOAPIC1  
VDDL1  
CPUCLK0  
VDDL0  
CPUCLK1  
CPUCLK2  
GNDL0  
GND5  
SDRAM0  
SDRAM1  
VDD5  
SDRAM2  
SDRAM3  
GND5  
SDRAM4  
SDRAM5  
VDD5  
SDRAM6  
SDRAM7  
GND5  
SDRAM_F  
VDD5  
PD#  
X1  
X2  
GND0  
GND1  
3V66-0  
3V66-1  
VDD1  
3
4
5
6
7
8
9
3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz  
achievable through I2C)  
9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz  
achievable through I2C)  
8 PCI (3.3 V) @33.3MHz  
VDD2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
2 IOAPIC (2.5V) @ 33.3MHz  
PCICLK0  
PCICLK1  
PCICLK2  
GND2  
PCICLK3  
PCICLK4  
GND2  
PCICLK5  
PCICLK6  
PCICLK7  
VDD2  
2 Hublink clocks (3.3 V) @ 66.6MHz  
2 USB (3.3V) @ 48MHz ( Non spread spectrum)  
1 REF (3.3V) @ 14.318MHz  
Features:  
Supports spread spectrum modulation,  
down spread 0 to -0.5% and ± 0.25% center spread.  
I2C support for power management  
VDD3  
GND3  
GND4  
Efficient power management scheme through PD#  
Uses external 14.138MHz crystal  
Alternate frequency selections available through I2C  
control.  
48MHz_0  
48MHz_1  
VDD4  
SCLK  
SDATA  
FS1  
FS0  
56-Pin 300mil SSOP  
* This input has a 50KW pull-down to GNDꢀ  
Block Diagram  
X1  
X2  
XTAL  
OSC  
REF0  
PLL1  
Spread  
Spectrum  
Functionality  
/2  
/3  
VDDL  
FS2  
FS1  
FS0  
Function  
CPU66/100/133 [2:0]  
3
2
8
1
8
X
X
0
0
0
1
Tristate  
Test  
FS(2:0)  
PD#  
Control  
Logic  
3V66 [1:0]  
SDRAM [7:0]  
SDRAM_F  
Active CPU = 66MHz  
SDRAM = 100MHz  
0
0
1
1
1
1
0
1
1
SDATA  
SCLK  
Active CPU = 100MHz  
SDRAM = 100MHz  
PCICLK [7:0]  
/2  
Config  
Reg  
Active CPU = 133MHz  
SDRAM = 100MHz  
IOAPIC [1:0]  
VDDL  
/2  
2
(Special Condition)  
Active CPU = 133MHz  
SDRAM = 133MHz  
PLL2  
48MHz [1:0]  
1
1
0
2
9250-16 Rev H 9/5/00  
Third party brands and names are the property of their respective owners.  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
information being relied upon by the customer is current and accurate.  

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