Integrated
Circuit
Systems, Inc.
ICS9250-09
Frequency Timing Generator for PENTIUM II Systems
General Description
Features
Generates the following system clocks:
The ICS9250-09 is a main clock synthesizer chip for
Pentium II based systems using Rambus Interface DRAMs.
This chip provides all the clocks required for such a system
when used with a Direct Rambus Clock Generator(DRCG)
chip such as the ICS9211-01.
- 4CPUclocks(2.5V,100/133MHz)
- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)
- 2CPU/2clocks(2.5V, 50/66MHz)
-3IOAPICclocks(2.5V,16.67MHz)
-4Fixedfrequency66MHzclocks(3.3V, 66MHz)
-2REFclocks(3.3V,14.318MHz)
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI
by 8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9250-09 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process
and temperature variations.
-1USBclock(3.3V,48MHz)
Efficient power management through PD#, CPU_STOP#
andPCI_STOP#.
0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
Usesexternal14.318MHzcrystal.
The CPU/2 clocks are inputs to the DRCG.
Key Specification
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCIOutputJitter:<500ps
Ref Output Jitter. <1000ps
Pin Configuration
CPU Output Skew: <175ps
CPU/2 Output Skew. <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66OutputSkew<250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Block Diagram
56-pin SSOP
9250-09 Rev J 1/21/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.