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ICS9248YG-150-T PDF预览

ICS9248YG-150-T

更新时间： 2024-09-24 22:09:47
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管服务器时钟
页数 文件大小 规格书
10页 155K
描述
Frequency Generator for Multi - Processor Servers

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中文翻译

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ICS9248YG-150-T 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-150  
FrequencyGeneratorforMulti-ProcessorServers  
Recommended Application:  
ServerWorks Grand Champion Systems.  
Pin Configuration  
Output Features:  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
PCICLK  
VDD48  
FS0/48MHz  
FS1/48MHz#  
GND48  
SEL100/133  
GNDPCI  
VDDA  
GNDA  
PD#  
•
•
•
8 - Differential CPU Clock Pairs @ 3.3V  
1 - 3V 33MHz PCI clocks  
1 - 48MHz clock  
VDDCPU  
CPUCLKT0  
CPUCLKC0  
GNDCPU  
CPUCLKT1  
CPUCLKC1  
VDDCPU  
CPUCLKT2  
CPUCLKC2  
GNDCPU  
CPUCLKT3  
CPUCLKC3  
VDDCPU  
REF  
VDDCPU  
CPUCLKT4  
CPUCLKC4  
GNDCPU  
CPUCLKT5  
CPUCLKC5  
VDDCPU  
CPUCLKT6  
CPUCLKC6  
GNDCPU  
CPUCLKT7  
CPUCLKC7  
VDDCPU  
MULTSEL0  
MULTSEL1  
GND  
•
•
1 - Inverted 48MHz clock  
1 - 14.318 reference output  
Features:  
•
•
•
Up to 200MHz frequency support  
Support power management: Power Down Mode  
Supports Spread Spectrum modulation: 0 to -0.5% down  
spread.  
•
•
Uses external 14.318MHz crystal  
Select logic for Differential Swing Control, Test mode,  
Tristate, Power down, Spread Spectrum.  
SPREAD#  
GNDREF  
X1  
X2  
VDDREF  
•
•
External resistor for current reference  
FS pins for frequency select  
GNDI REF  
I REF  
VDDI REF  
Key Specifications:  
•
•
•
•
PCI Output jitter <500ps  
CPU Output jitter <200ps  
48MHz Output jitter <350ps  
REF Output jitter < 1000ps  
48-Pin SSOP and TSSOP  
Functionality  
Block Diagram  
SEL133/  
100  
FS0 FS1  
Function  
PLL2  
48MHz  
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Active 100MHz  
100MHz Test Mode  
100MHz Test Mode  
Tristate all outputs  
Active 133MHz  
133MHz Test Mode  
Active 200MHz  
Reserved  
48MHz#  
0
X1  
X2  
XTAL  
OSC  
0
REF  
0
1
PLL1  
Spread  
Spectrum  
CPUCLKT (7:0)  
CPUCLKC (7:0)  
CPU  
DIVDER  
8
1
8
1
PCI  
DIVDER  
PCICLK  
1
PD#  
SPREAD#  
Control  
Logic  
MULTSEL(1:0)  
SEL100/133  
FS(1:0)  
Analog Power Groups  
VDD48, GND48=48MHz, PLL2  
VDDA=VDD (core supply voltage 3.3V)  
GNDA=Ground for core supply  
Config.  
Reg.  
I REF  
Digital Power Group  
VDDREF, GNDREF=REF, Xtal  
ICS reserves the right to make changes in the device data  
identified in this publication without further notice. ICS advises  
its customers to obtain the latest version of all device data to  
verify that any information being relied upon by the customer is  
9248-150 Rev B 06/12/01  
Third party brands and names are the property of their respective owners.  
1234567...10

中文翻译

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 		Processor Specific Clock Generator, 133.33MHz, PDSO28, 4.40 MM, 0.65 MM PITCH, TSSOP-28
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 		Processor Specific Clock Generator, 133.33MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, TSSOP-48
ICS9248YG-189-T IDT

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 		Processor Specific Clock Generator, 133.33MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, TSSOP-48

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