ICS9248-87
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Pin Configuration
Output Features:
•
•
•
•
•
•
•
•
2- CPUs @2.5V, up to 155MHz.
9 - SDRAM @ 3.3V, up to 155MHz.
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V
2- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V
1- REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 155MHz frequency support
Support FS0-FS3 strapping status bit for I2C read back.
Support power management: Power down Mode from I2C
programming.
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
Skew Specifications:
48-Pin 300mil SSOP
*: These inputs have a 120K pull up to VDD.
1: These are double strength.
•
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
For group skew specification, please refer to group
timing relationships table.
Block Diagram
Functionality
PCICLK IOAPIC
PLL2
48MHz
IOAPIC
(PCI)
(MHz)
2
CPU
CPU/
SDRAM 3V66
(3V66*
1/2)
(PCI*
1/2)
FS3 FS2 FS1 FS0
24_48MHz
(MHz) SDRAM (MHz)
(MHz)
/ 2
(MHz)
(MHz)
X1
X2
XTAL
OSC
83.3
1.00
83.3
55.48
82.67
27.74
41.33
51.67
36.00
35.00
37.33
50.00
35.00
34.17
35.67
46.00
34.34
33.40
33.40
44.53
33.40
13.87
20.67
25.83
18.00
17.50
18.67
25.00
17.50
17.08
17.83
23.00
17.17
16.70
16.70
22.27
16.70
27.74
41.33
51.67
36.00
35.00
37.33
50.00
35.00
34.17
35.67
46.00
34.34
33.40
33.40
44.53
33.40
REF1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
124.00
155.00
143.96
70.00
1.00 124.00
1.00 155.00 103.33
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK [1:0]
2
8
1.33 108.00
0.67 105.00
1.00 112.00
72.00
70.00
74.67
SDRAM
DIVDER
112.00
150.00
140.00
68.33
SDRAM [7:0]
SDRAM_F
1.00 150.00 100.00
SEL24_48#
SDATA
1.33 105.00
0.67 102.50
1.00 107.00
1.00 138.00
1.33 103.00
0.67 100.20
1.00 100.30
1.00 133.60
1.33 100.20
70.00
68.33
71.33
92.00
68.67
66.80
66.80
89.07
66.80
Control
Logic
I2C
{
IOAPIC
DIVDER
SCLK
IOAPIC
107.00
138.00
137.33
66.80
FS[3:0]
PCI
DIVDER
PD#
PCICLK [7:0]
8
2
Config.
Reg.
100.30
133.60
133.60
3V66
DIVDER
3V66 [1:0]
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248-87 Rev D 10/27/00
Third party brands and names are the property of their respective owners.