Datasheet > ICS9214YGLF-T

ICS9214YGLF-T

更新时间： 2024-09-29 03:11:59

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器
页数	文件大小	规格书
16页	236K
描述
RambusTM XDRTM Clock Generator

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中文翻译

获取价格

数据手册

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ICS9214YGLF-T 数据手册

Integrated

Circuit

ICS9214

Systems, Inc.

Rambus^TMXDR^TMClock Generator

General Description

Features

•

400 – 500 MHz clock source

4 open-drain differential output drives with short term

jitter < 40ps

Spread spectrum compatible

Reference clock is differential or single-ended, 100 or

133 MHz

The ICS9214 clock generator provides the necessary clock

signals to support the Rambus XDR^TMmemory subsystem

and Redwood logic interface. The clock source is a reference

clock that may or may not be modulated for spread spectrum.

The ICS9214 provides 4 differential clock pairs in a space

saving 28-pin TSSOP package and provides an off-the-shelf

high-performance interface solution.

•

SMBus programmability for:

- frequency multiplier

- output enable

- operating mode

Supports frequency multipliers of: 3, 4, 5, 6, 8, 9/2,

15/2 and 15/4

Support systems where XDR subsystem is

asynchronous to other system clocks

2.5V power supply

Figure 1 shows the major components of the ICS9214 XDR

Clock Generator. These include the a PLL, a Bypass

Multiplexer and four differential output buffers. The outputs

can be disabled by a logic low on the OE pin. An output is

enabled by the combination of the OE pin being high, and 1

in its SMBus Output control register bit.

•

The PLL receives a reference clock, CLK_INT/C and outputs

a clock signal at a frequency equal to the input frequency

times a multiplier. Table 2 shows the multipliers selectable

via the SMBus interface. This clock signal is then fed to the

differential output buffers to drive the enabled clocks. Disabled

outputs are set to Hi-Z. The Bypass mode routes the input

clock, CLK_INT/C, directly to the differential output buffers,

bypassing the PLL.

Up to four ICS9214 devices can be cascaded on the same

SMBus. Table 3 shows the SMBus addressing and control for

the four devices.

Block Diagram

Pin Configuration

AVDD2.5

AGND

IREFY

28 VDD2.5

RegA

27 ODCLK_T0

26 ODCLK_C0

25 GND

24 ODCLK_T1

23 ODCLK_C1

22 VDD2.5

ODCLK_T0

BYPASS#/PLL

ODCLK_C0

AGND

Bypass

MUX

CLK_INT

CLK_INC

VDD2.5

GND

SMBCLK

SMBDAT 10

OE 11

RegB

ODCLK_T1

ODCLK_C1

CLK_INT

CLK_INC

PLL

21 GND

RegC

20 ODCLK_T2

19 ODCLK_C2

18 GND

ODCLK_T2

ODCLK_C2

SMB_A0 12

SMB_A1 13

BYPASS#/PLL 14

17 ODCLK_T3

16 ODCLK_C3

15 VDD2.5

SMBCLK

RegD

ODCLK_T3

ODCLK_C3

28-Pin 4.4mm TSSOP

SMBDAT SMB_A0 SMB_A1

0809F–11/05/07

12 3 4 5 6 7...16

中文翻译

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与ICS9214YGLF-T相关器件

型号	品牌	获取价格	描述	数据表
ICS9214YG-T	IDT	获取价格	PLL Based Clock Driver, 9214 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.173
ICS9219	ICSI	获取价格	Direct Rambus Clock Generator Lite
ICS9219GLF-T	IDT	获取价格	Clock Generator, PDSO16
ICS9219G-T	IDT	获取价格	Clock Generator, PDSO16
ICS9219YGLF-T	ICSI	获取价格	Direct Rambus Clock Generator Lite
ICS9219YG-T	IDT	获取价格	Processor Specific Clock Generator, 533.3MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153, TSSO
ICS9220	IDT	获取价格	Programmable RambusTM XDRTM Clock Generator
ICS9220B	IDT	获取价格	Programmable RambusTM XDRTM Clock Generator
ICS9220YGLF-T	IDT	获取价格	Processor Specific Clock Generator, PDSO28, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153
ICS9222-01	ICSI	获取价格	Dual Memory Clock Generator

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