Datasheet > ICS9214G

ICS9214G

更新时间： 2024-09-29 14:51:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	212K
描述
Clock Generator

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ICS9214G 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

ICS9214G 数据手册

ICS9214

Advance Information

Integrated

Circuit

Systems, Inc.

Rambus^TM800 MHz XDR^TMClock Generator

General Description

Features

•

400 – 500 MHz clock source

The ICS9214 clock generator provides the necessary

clock signals to support the Rambus XDR^TMmemory

subsystem and Redwood logic interface. The clock

source is a reference clock that may or may not be

modulated for spread spectrum. The ICS9214 provides 4

differential clock pairs in a space saving 28-pin TSSOP

package and provides an off-the-shelf high-performance

interface solution.

4 open-drain differential output drives with short

term jitter < 40ps

•

Spread spectrum compatible

Reference clock is differential or single-ended, 100

or 133 MHz

•

SMBus programmability for:

- frequency multiplier

- output enable

Figure 1 shows the major components of the ICS9214

XDR Clock Generator. These include the a PLL, a Bypass

Multiplexer and four differential output buffers. The outputs

can be disabled by a logic low on the OE pin. An output

is enabled by the combination of the OE pin being high,

and 1 in its SMBus Output control register bit.

- operating mode

•

Supports frequency multipliers of: 3, 4, 5, 6, 8,

9/2, 15/2 and 15/4

Support systems where XDR subsystem is

asynchronous to other system clocks

The PLL receives a reference clock, CLK_INT/C and

outputs a clock signal at a frequency equal to the input

frequency times a multiplier. Table 2 shows the multipliers

selectable via the SMBus interface. This clock signal is

then fed to the differential output buffers to drive the

enabled clocks. Disabled outputs are set to Hi-Z. The

Bypass mode routes the input clock, CLK_INT/C, directly

to the differential output buffers, bypassing the PLL.

2.5V power supply

Up to four ICS9214 devices can be cascaded on the same

SMBus. Table 3 shows the SMBus addressing and control

for the four devices.

Block Diagram

Pin Configuration

AVDD2.5

AGND

28 VDD2.5

27 ODCLK_T0

26 ODCLK_C0

25 GND

24 ODCLK_T1

23 ODCLK_C1

22 VDD2.5

RegA

IREFY

AGND

CLK_INT

CLK_INC

VDD2.5

GND

SMBCLK

SMBDAT 10

OE 11

SMB_A0 12

SMB_A1 13

ODCLK_T0

BYPASS#/PLL

ODCLK_C0

Bypass

MUX

RegB

ODCLK_T1

ODCLK_C1

CLK_INT

CLK_INC

PLL

21 GND

RegC

20 ODCLK_T2

19 ODCLK_C2

18 GND

17 ODCLK_T3

16 ODCLK_C3

15 VDD2.5

ODCLK_T2

ODCLK_C2

SMBCLK

RegD

ODCLK_T3

ODCLK_C3

BYPASS#/PLL 14

SMBDAT SMB_A0 SMB_A1

28-Pin 4.4mm TSSOP

0809—08/26/04

XDR is a trademark of Rambus

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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与ICS9214G相关器件

型号	品牌	获取价格	描述	数据表
ICS9214GLF	IDT	获取价格	Clock Generator
ICS9214YGLF-T	ICSI	获取价格	Rambus XDR Clock Generator
ICS9214YGLF-T	ICSI	获取价格	RambusTM XDRTM Clock Generator
ICS9214YG-T	IDT	获取价格	PLL Based Clock Driver, 9214 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.173
ICS9219	ICSI	获取价格	Direct Rambus Clock Generator Lite
ICS9219GLF-T	IDT	获取价格	Clock Generator, PDSO16
ICS9219G-T	IDT	获取价格	Clock Generator, PDSO16
ICS9219YGLF-T	ICSI	获取价格	Direct Rambus Clock Generator Lite
ICS9219YG-T	IDT	获取价格	Processor Specific Clock Generator, 533.3MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153, TSSO
ICS9220	IDT	获取价格	Programmable RambusTM XDRTM Clock Generator

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