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ICS9212YF-03-T PDF预览

ICS9212YF-03-T

更新时间: 2024-11-12 09:59:47
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
7页 133K
描述
Processor Specific Clock Generator, 400MHz, PDSO24, 0.150 INCH, MO-137, SSOP-24

ICS9212YF-03-T 数据手册

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ICS9212-03  
Integrated  
Circuit  
Systems, Inc.  
Direct Rambus™ Clock Generator  
General Description  
Features  
Compatible with all Direct Rambus™ based IC s  
Up to 400 MHz differential clock source for direct  
Rambus™ memory system  
Cycle to cycle jitter is less than 50ps  
3.3 + 5% supply  
Synchronization flexibility: Supports Systems that  
need clock domains of Rambus channel to  
synchronize with system or processor clock, or  
systems that do not require synchronization of the  
Rambus clock to another system clock  
The ICS9212-03 is a High-speed clock generator providing  
400 MHz differential clock source for direct Rambus  
memory system. It includes DDLL (Distributed Delay  
locked loop) and phase detection mechanism to  
synchronize the direct Rambuschannel clock to an  
external system clock. ICS9212-03 provides a solution for  
a broad range of Direct Rambus memory applications.The  
device works in conjunction with the ICS9250-09.  
The ICS9212-03 power management support system  
turns “off” the Rambuschannel clock to minimize power  
consumption for mobile and other power –sensitive  
applications. In “clock off” mode the device remains “on”  
while the output is disabled, allowing fast transitions  
between clock-off and clock –on states. In “power down”  
mode it completely powers down for minimum power  
dissipation.  
Excellent power management support  
REFCLK input is from the ICS9250-09.  
TheICS9212-03meetstherequirementsforinputfrequency  
tracking when the input frequency clock is using Spread  
Spectrum clocking and also the optimum bandwidth is  
maintained while attenuating the jitter of the reference  
signal.  
Block Diagram  
Pin Configuration  
VDDREF  
REFCLK  
VDD1  
GND1  
GND3  
PCLK/M  
SYNCLK/N  
GND2  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
FS0  
FS1  
BUSCLK_STOP#  
VDD-OUT  
GND-OUT  
BUSCLKT  
N/C  
BUSCLKC  
GND-OUT  
VDD-OUT  
MULTI0  
MULTI1  
GND3  
PD#  
FS(0:1)  
Test MUX  
Bypass MUX  
GND  
Bypclk  
PLLclk  
PLL  
VDD2  
VDDPD  
BUSCLK_STOP#  
PD#  
Refclk  
B
A
BUSCLKT  
BUSCLKC  
Phase  
Aligner  
10  
11  
12  
PAclk  
GND  
Phase  
Detector  
Multi(0:1)  
24-Pin 150 Mil SSOP  
2
Pclk/M  
Synclk/N  
0270G—05/24/05  

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