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ICS9212YF-01LF PDF预览

ICS9212YF-01LF

更新时间： 2024-11-11 20:11:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路
页数 文件大小 规格书
6页 144K
描述
Processor Specific Clock Generator, 400MHz, PDSO24, 0.150 INCH, SSOP-24

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中文翻译

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ICS9212YF-01LF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.19
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：8.65 mm端子数量：24
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：400 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压：3.45 V最小供电电压：3.15 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

ICS9212YF-01LF 数据手册

 浏览型号ICS9212YF-01LF的Datasheet PDF文件第2页浏览型号ICS9212YF-01LF的Datasheet PDF文件第3页浏览型号ICS9212YF-01LF的Datasheet PDF文件第4页浏览型号ICS9212YF-01LF的Datasheet PDF文件第5页浏览型号ICS9212YF-01LF的Datasheet PDF文件第6页 
ICS9212-01  
Integrated  
Circuit  
Systems, Inc.  
Preliminary Product Preview  
Direct Rambus™ Clock Generator  
General Description  
Features  
•
•
Compatible with all Direct Rambus™ based IC s  
The ICS9212-01 is a High-speed clock generator providing  
400 MHz differential clock source for direct RambusÔ  
memory system. It includes DDLL (Distributed Delay locked  
loop) and phase detection mechanism to synchronize the  
direct RambusÔ channel clock to an external system clock.  
ICS9212-01 provides a solution for a broad range of Direct  
Rambus memory applications. The device works in  
conjunction with the ICS9250-09.  
Up to 400 MHz differential clock source for direct  
Rambus™ memory system  
•
•
•
Cycle to cycle jitter is less than 50ps  
3.3 + 5% supply  
Synchronization flexibility: Supports Systems that  
need clock domains of Rambus channel to synchronize  
with system or processor clock, or systems that do not  
require synchronization of the Rambus clock to  
another system clock  
The ICS9212-01 power management support system turns  
“off” the RambusÔ channel clock to minimize power  
consumption for mobile and other power –sensitive  
applications. In “clock off” mode the device remains “on”  
while the output is disabled, allowing fast transitions between  
clock-off and clock –on states. In “power down” mode it  
completely powers down for minimum power dissipation.  
•
•
Excellent power management support  
REFCLK input is from the ICS9250-09.  
The ICS9212-01 meets the requirements for input frequency  
tracking when the input frequency clock is using Spread  
Spectrum clocking and also the optimum bandwidth is  
maintained while attenuating the jitter of the reference signal.  
Block Diagram  
Pin Configuration  
VDDREF  
REFCLK  
VDD1  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
FS0  
BUSCLK_STOP#  
FS1  
3
VDD-OUT  
GND-OUT  
BUSCLKT  
N/C  
PD#  
GND1  
4
FS(0:1)  
GND3  
5
Test MUX  
Bypass MUX  
PCLK/M  
SYNCLK/N  
GND2  
6
GND  
Bypclk  
7
BUSCLKC  
GND-OUT  
VDD-OUT  
MULTI0  
MULTI1  
GND3  
8
PLLclk  
PLL  
VDD2  
9
Refclk  
B
A
VDDPD  
10  
11  
12  
BUSCLKT  
BUSCLKC  
Phase  
Aligner  
BUSCLK_STOP#  
PD#  
PAclk  
GND  
Phase  
Detector  
24-Pin 150 Mil SSOP  
Multi(0:1)  
2
Pclk/M  
Synclk/N  
PRODUCT PREVIEW documents contain information on new  
products in the sampling or preproduction phase of development.  
Characteristic data and other specifications are subject to change  
without notice.  
9212-01RevC3/6/00  
123456

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ICS9212YF-03LF-T IDT

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 		Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, SSOP-56
ICS9212YF-12LF-T IDT

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 		Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, SSOP-56
ICS9212YF-13LF ICSI

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 		Direct Rambus⑩ Clock Generator

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