PRELIMINARY
ICS8MX0
Integrated
Circuit
Systems, Inc.
LVCMOS/LVTTL CLOCK OSCILLATOR
ICS8MX0
LOW JITTER, HIGH FREQUENCY XTAL OSCILLATOR
• Stable, ultra low jitter, LVCMOS/LVTTL clock generation
• For Gigabit Ethernet, Fibre Channel, PCI-Express, other applications
• Clock output frequencies from 75MHz to 250MHz
• One single-ended LVCMOS/LVTTL clock output
• Output Enable (OE) pin (high impedance – when low)
• Small 4-pin 5mm x 7mm x 1.5mm SMT ceramic package
• Low profile package allows back-side PCB mounting
• Pb-free RoHS compliant (by default; no additional code required)
• 3.3V or 2.5V device power supply options
8Mx0
(Top View )
O
O
• Commercial (0 to +70 C) and Industrial (-40 to +85 C) temperatures
• Frequency stability of 50ppm or 100ppm
(including initial accuracy, operating temperature variation, supply voltage
variation, load variation, reflow drift, and aging for 10 years)
• Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)
4-pin CERHERMETIC 5mm x 7mm x 1.5mm SMT
ELECTRICAL SPECIFICATIONS
Unless stated otherwise, VDD = 3.3V 0.3V or 2.5V 5ꢀ, TA = 0°C to +70°C (commercial), TA = -40°C to +85°C (industrial)
Specifications
Min.
Typ.
Max.
Units
Item
Symbol
Test Conditions
DC Characteristics
Power Supply
(VDD, GND pins)
3.0
3.3
2.5
75
3.6
V
V
3.3V operation
Power Supply Voltage
VDD
2.375
2.625
2.5V operation (8MJ0 and 8MK0 only)
Power Supply Current
Current w/Output Disabled
Input Capacitance
IDD
mA
mA
pF
V
OE = VDD
IOED
CIN
VIH
<0.6
OE = GND
4
Output Enable
(OE pin)
LVCMOS/LVTTL
Input High Voltage
0.7 * VDD
Input Low Voltage
VIL
0.3 * VDD
5
V
Input High Current
IIH
µA
µA
VDD = VIN = 3.6V or 2.625V
Input Low Current
IIL
-150
VDD = 3.6V or 2.625V, VIN = 0V
Internal Pullup Resistor
Output High Voltage1
Output Low Voltage1
Output Load Condition
Output Impedance
RPULLUP
VOH
VOL
CL
51
20
kΩ
Clock Output
Level (OUT pin)
LVCMOS/LVTTL
VDD - 0.4
V
V
VDD = 3.3V 0.3V or 2.5V 5ꢀ
0.4
25
pF
Ω
fO ≤ 250MHz
ROUT
AC Characteristics
Output
(OUT pin)
Output Frequency Range
75
250
100
50
MHz
All conditions
ppm p-p 8MH0 & 8MK0
ppm p-p 8MG0 & 8MJ0
Includes frequency set, VDD, T
load variation, reflow drift, 10 yr. aging
≤ Max. pF
A and
Frequency Stability Error
Δ
f/fO
Output Duty Cycle
Output Rise Time
Output Fall Time
odc
tR
50
ꢀ
ns
VTH = VDD / 2, CL
1.5
1.5
10
20ꢀ to 80ꢀ of VDD CL
≤
Max. pF
tF
ns
Oscillator Start-up Time
RMS Phase Jitter, Random2 t jit (Ø)
tOSC
ms
ps rms
ps
Time at Min. VDD (3.0V or 2.375V) to be 0s
design target
<1
3
Jitter
tDS
tRS
0.2
3
Deterministic
3
ps
ps
ps
ps
Random, σ of random jitter
3
tRMS
3
Root Mean Square,
Peak-to-Peak
σ of total jitter distribution
3
tP-P
25
4
3
tacc
Accumulated Jitter, n = 2 to 50,000 cycles
NOTE 1: Outputs terminated with 50
NOTE 2: Measured using an Aeroflex PN9500 with a 12kHz to 20MHz integration range.
NOTE 3: Measured using a Wavecrest SIA-3000.
Ω to VDD/2. See Parameter Measurement Information, Output Load AC Test Circuit Diagrams.
Supply Voltage & Frequency Accuracy
G =
H =
J =
3.3V / 3.3V
3.3V / 3.3V
2.5V / 3.3V
2.5V / 3.3V
50 ppm
100 ppm
50 ppm
The Preliminary Information presented herein represents a product in prototyping or pre-production. The
noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorpo-
rated (ICS) reserves the right to change any circuitry or specifications without notice.
K =
100 ppm
8Mx0AJ
www.icst.com/products/hiperclocks.html
REV.C NOVEMBER 18, 2005
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