Datasheet > ICS8701-01

ICS8701-01

更新时间： 2024-09-25 22:40:19

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器
页数	文件大小	规格书
10页	210K
描述
LOW SKEW ±1, ±2 CLOCK GENERATOR W/POLARITY CONTROL

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ICS8701-01 数据手册

ICS8701-01

L^OWSKEW ¸1, ¸2 CLOCK

Integrated

Circuit

Systems, Inc.

GENERATOR W/POLARITY CONTROL

GENERAL DESCRIPTION

FEATURES

The ICS8701-01 is a low skew, ÷1, ÷2 Clock 20 LVCMOS outputs, 7Ω typical output impedance

,&6

Generator and a member of the HiPerClockS

family of High Performance Colck Solutions

Output frequency up to 250 MHz

HiPerClockS™

from ICS. The low impedance LVCMOS outputs

are designed to drive 50Ω series or parallel ter-

250ps bank skew, 300ps output skew, 350ps multiple

frequency skew, 700ps part-to-part skew

minated transmission lines. The effective fanout can be in-

creased from 20 to 40 by utilizing the ability of the outputs to

drive two series terminated lines.

Selectable inverting and non-inverting outputs

LVCMOS / LVTTLclock input

The divide select inputs, DIV_SELx, control the output fre-

quency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The master reset/

output enable input, nMR/OE, resets the internal dividers and

controls the active and high impedance states of all outputs.

The output polarity inputs, INV0:1, control the polarity (invert-

ing or non-inverting) of the outputs of each bank. Outputs

QA0-QA4 are inverting for every combination of the INV0:1

input. The timing relationship between the inverting and non-

inverting outputs at different frequencies is shown in the Tim-

ing Diagrams.

LVCMOS / LVTTLcontrol inputs

Bank enable logic allows unused banks to be disabled

in reduced fanout applications

3.3V or mixed 3.3V input, 2.5V output operating

supply modes

48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm

package body, 0.5mm package lead pitch

0°C to 70°C ambient operating temperature

Other divide values available on request

The ICS8701-01 is characterized at 3.3V and mixed 3.3V in-

put supply, and 2.5V output supply operating modes. Guar-

anteed bank, output and part-to-part skew characteristics

make the ICS8701-01 ideal for those clock distribution appli-

cations demanding well defined performance and repeatabil-

ity.

BLOCK DIAGRAM

PIN ASSIGNMENT

÷1

÷2

LVCMOS_CLK

DIV_SELA

QAO - QA4

QB0 - QB4

QC0 - QC4

QD0 - QD4

48 47 46 45 44 43 42 41 40 39 38 37

QC3

VDDOC

QC4

QB1

VDDOB

QB0

QD0

QA4

DIV_SELB

DIV_SELC

VDDOD

QD1

VDDOA

QA3

ICS8701-01

GND

QA2

QD2

GND

QA1

QD3

VDDOD

QD4

VDDOA

QA0

13 14 15 16 17 18 19 20 21 22 23 24

DIV_SELD

nMR/OE

Output

Polarity

Control

INV0

INV1

48-Pin LQFP

Y Package

Top View

8701-01

www.icst.com

REV. A - AUGUST 28, 2000

12 3 4 5 6 7...10

中文翻译

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与ICS8701-01相关器件

型号	品牌	获取价格	描述	数据表
ICS8701-01AY	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701-01AYLF	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701-01AY-T	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701-01Y	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR W/POLARITY CO
ICS8701-01YLF	IDT	获取价格	Clock Generator, 250MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-48
ICS8701-01YT	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR W/POLARITY CO
ICS87016AY	IDT	获取价格	Low Skew Clock Driver, 87016 Series, 16 True Output(s), 0 Inverted Output(s), CMOS, 7 X 7
ICS8701AY-01	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), CMOS, PQFP48, 7 X 7 MM, 1.
ICS8701AY-01LF	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701AY-01LFT	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM

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