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ICS854S204AGILF PDF预览

ICS854S204AGILF

更新时间: 2024-11-11 20:11:07
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 3231K
描述
Low Skew Clock Driver, 854 Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-16

ICS854S204AGILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:854输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:2反相输出次数:
端子数量:16实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

ICS854S204AGILF 数据手册

 浏览型号ICS854S204AGILF的Datasheet PDF文件第2页浏览型号ICS854S204AGILF的Datasheet PDF文件第3页浏览型号ICS854S204AGILF的Datasheet PDF文件第4页浏览型号ICS854S204AGILF的Datasheet PDF文件第5页浏览型号ICS854S204AGILF的Datasheet PDF文件第6页浏览型号ICS854S204AGILF的Datasheet PDF文件第7页 
PRELIMINARY  
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-  
TO-LVDS, LVPECL FANOUT BUFFER  
ICS854S204I  
GENERAL DESCRIPTION  
FEATURES  
The ICS854S204I is a low skew, high performance  
Two differential LVDS or LVPECL output banks  
ICS  
dual, 1-to-2 Differential-to-LVDS, LVPECL Fanout  
Buffer and a member of the HiPerClockS™fam-  
ily of High Performance Clock Solutions from IDT.  
The CLKx, nCLKx pairs can accept most standard  
Two differential clock input pairs  
HiPerClockS™  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
differential input levels. The ICS854S204I is characterized to  
operate from either a 2.5V or a 3.3V power supply. Guaran-  
teed output and bank skew characteristics make the  
ICS854S204I ideal for those clock distribution applications  
demanding well defined performance and repeatability.  
Maximum output frequency: >3GHz  
Translates any single ended input signal to LVDS levels  
with resistor bias on nCLKx inputs  
Output skew: <25ps (typical) design target  
Bank skew: <50ps (typical) design target  
Propagation delay: TBD  
Additive phase jitter, RMS: 0.15ps (typical)  
Full 3.3V or 2.5V power supply  
-40°C to 85°C ambient operating temperature  
SUPPLY MODE OPERATION TABLE  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
3.3V Operation  
2.5V Operation  
VDD = 2.5V  
VDD = 3.3V  
V
TAP = nc  
VTAP = 2.5V  
SEL_OUT FUNCTION TABLE  
SEL_OUT  
Output Level  
0
1
LVDS  
LVPECL  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VTAP  
CLKA  
nCLKA  
QA0  
nQA0  
QA1  
nQA1  
VTAP  
GND  
1
2
3
4
5
6
7
8
nCLKB  
CLKB  
QB0  
nQB0  
QB1  
nQB1  
VDD  
SEL_OUT  
16  
15  
14  
13  
12  
11  
10  
9
Pulldown  
SEL_OUT  
QA0  
Pulldown  
CLKA  
nQA0  
Pullup  
nCLKA  
QA1  
nQA1  
QB0  
Pulldown  
CLKB  
nQB0  
Pullup  
ICS854S204I  
16-Lead TSSOP  
nCLKB  
QB1  
nQB1  
4.4mm x 5.0mm x 0.92mm package body  
G Package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product  
characterization. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT/ ICSLVDS, LVPECL FANOUT BUFFER  
1
ICS854S204AGI REVAAUGUST 14, 2006  

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