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ICS854105AGLF PDF预览

ICS854105AGLF

更新时间: 2024-11-11 19:58:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 665K
描述
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16

ICS854105AGLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:854104输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:4
端子数量:16实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

ICS854105AGLF 数据手册

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ICS854105  
Low Skew, 1-to-4, LVCMOS/LVTTL-to-  
LVDS Fanout Buffer  
DATA SHEET  
General Description  
Features  
The ICS854105 is a low skew, high performance  
1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer.  
Utilizing Low Voltage Differential Signaling (LVDS), the  
ICS854105 provides a low power, low noise solution  
for distributing clock signals over controlled  
Four differential LVDS output pairs  
S
IC  
One single-ended LVCMOS/LVTTL input  
HiPerClockS™  
CLK can accept the following input levels: LVCMOS, LVTTL  
Maximum output frequency: 250MHz  
Translates single-ended input signals to LVDS levels  
Additive phase jitter, RMS: 0.16ps (typical)  
Output skew: 55ps (maximum)  
impedances of 100. The ICS854105 accepts an LVCMOS/LVTTL  
input level and translates it to LVDS output levels.  
Guaranteed output and part-to-part skew characteristics make the  
ICS854105 ideal for those applications demanding well defined  
performance and repeatability.  
Part-to-part skew: 350ps (maximum)  
Propagation delay: 1.62ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Block Diagram  
Pin Assignment  
Q0  
OE0  
OE1  
OE2  
VDD  
Q0  
1
2
3
4
5
6
7
8
16  
15  
nQ0  
nQ0  
14 Q1  
Pullup  
OE0  
13  
12  
11  
10  
9
nQ1  
Q2  
GND  
CLK  
nc  
Q1  
nQ2  
Q3  
nQ1  
nQ3  
OE3  
Pullup  
OE1  
Pulldown  
CLK  
ICS854105  
Q2  
16-Lead TSSOP  
4.4mm x 5.0mm x 0.925mm package body  
G Package  
nQ2  
OE2  
Pullup  
Pullup  
Top View  
Q3  
nQ3  
OE3  
ICS854105AG REVISION A FEBRUARY 23, 2010  
1
©2010 Integrated Device Technology, Inc.  

ICS854105AGLF 替代型号

型号 品牌 替代类型 描述 数据表
ICS854104AGLFT IDT

完全替代

Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40
ICS854104AG IDT

完全替代

Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40
ICS854104AGT IDT

完全替代

Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40

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