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ICS85357AG-01 PDF预览

ICS85357AG-01

更新时间: 2024-11-08 22:22:31
品牌 Logo 应用领域
矽成 - ICSI 复用器时钟
页数 文件大小 规格书
12页 122K
描述
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

ICS85357AG-01 数据手册

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ICS85357-01  
4:1 OR 2:1  
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS85357-01 is a 4:1 or 2:1 Differential-to- High speed differential multiplexer. The device can be  
3.3V LVPECL / ECL clock multiplexer which can  
operate up to 750MHz and is a member of the  
HiPerClockS™ family of High Performance Clock  
Solutions from ICS. The ICS85357-01 has 4  
configured as either a 4:1 or 2:1 multiplexer  
1 differential 3.3V LVPECLoutput  
4 selectable CLK, nCLK inputs  
HiPerClockS™  
selectable clock inputs. The CLK, nCLK pair can accept most  
standard differential input levels. The device can operate  
using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or  
3.3V ECL (VCC = 0V, VEE = -3.135V to -3.465V). The fully dif-  
ferential architecture and low propagation delay make it  
ideal for use in clock distribution circuits. The select pins have  
internal pulldown resistors. Leaving one input unconnected  
(pulled to logic low by the internal resistor) will transform  
the device into a 2:1 multiplexer. The SEL1 pin is the most  
significant bit and the binary number applied to the select pins  
will select the same numbered data input (i.e., 00  
selects CLK0, nCLK0).  
CLK, nCLK pair can accept the following differential input  
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum output frequency up to 750MHz  
Translates any single ended input signal to 3.3V LVPECL  
levels with resistor bias on nCLKx input  
Part-to-part skew: 150ps (maximum)  
Propagation delay: 1.5ns (maximum)  
LVPECLmode operating voltage supply range:  
VCC = 3.135V to 3.465V, VEE = 0V  
ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3.135V to -3.465V  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCC  
CLK0  
nCLK0  
CLK1  
nCLK1  
CLK2  
nCLK2  
CLK3  
nCLK3  
VEE  
1
2
3
4
5
6
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
SEL1  
SEL0  
VCC  
Q0  
CLK0  
00  
nCLK0  
CLK1  
01  
nCLK1  
Q0  
nQ0  
nQ0  
VCC  
nc  
nc  
VEE  
CLK2  
10  
7
8
9
10  
nCLK2  
CLK3  
11  
nCLK3  
ICS85357-01  
20-Lead TSSOP  
4ꢀ40mm x 6ꢀ50mm x 0ꢀ90mm body package  
G Package  
SEL0  
SEL1  
Top View  
85357AG-01  
www.icst.com/products/hiperclocks.html  
REV. A JULY 16, 2001  
1

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