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ICS8535-21 PDF预览

ICS8535-21

更新时间: 2024-11-05 22:55:27
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
14页 226K
描述
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER

ICS8535-21 数据手册

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ICS8535-21  
Integrated  
Circuit  
Systems, Inc.  
LOW  
S
KEW, 1-TO-2  
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT  
BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8535-21 is a low skew, high performance 2 differential 3.3V LVPECL outputs  
ICS  
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout  
Selectable CLK0 or CLK1 inputs for redundant  
buffer and a member of the HiPerClockSfam-  
and multiple frequency fanout applications  
HiPerClockS™  
ily of High Performance Clock Solutions from  
ICS.The ICS8535-21 has two single-ended clock  
CLK0 or CLK1 can accept the following input levels:  
inputs. The single-ended clock input accepts LVCMOS or  
LVTTL input levels and translate them to 3.3V LVPECL lev-  
els. The clock enable is internally synchronized to eliminate  
runt clock pulses on the output during asynchronous asser-  
tion/deassertion of the clock enable pin.  
LVCMOS or LVTTL  
Maximum output frequency: 266MHz  
Translates LVCMOS and LVTTL levels to  
3.3V LVPECL levels  
Guaranteed output and part-to-part skew characteristics  
make the ICS8535-21 ideal for those applications demand-  
ing well defined performance and repeatability.  
Output skew: 20ps (maximum)  
Part-to-part skew: 300ps (maximum)  
Propagation delay: 1.6ns (maximum)  
Additive phase jitter, RMS: 0.03ps (typical)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
D
CLK_EN  
Q
1
2
3
4
5
6
7
VEE  
CLK_EN  
CLK_SEL  
CLK0  
14  
13  
12  
11  
10  
9
VCC  
Q0  
nQ0  
nc  
Q1  
nQ1  
VCC  
LE  
CLK0  
CLK1  
0
1
Q0  
nQ0  
VEE  
CLK1  
VCC  
Q1  
nQ1  
8
CLK_SEL  
ICS8535-21  
14-LeadTSSOP  
4.4mm x 5.0mm x 0.92mm body package  
G Package  
Top View  
8535AG-21  
www.icst.com/products/hiperclocks.html  
REV. A OCTOBER 20, 2004  
1

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