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ICS8432DY-101T PDF预览

ICS8432DY-101T

更新时间: 2024-09-17 11:14:39
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
18页 197K
描述
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432DY-101T 数据手册

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ICS8432-101  
700MHZ,  
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8432-101 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs  
ICS  
put Differential-to-3.3V LVPECL high frequency  
Selectable CLK, nCLK or LVCMOS/LVTTLTEST_CLK  
HiPerClockS™  
synthesizer and a member of the HiPerClockS™  
family of High Performance Clock Solutions from  
ICS. The ICS8432-101 has a selectable  
TEST_CLK can accept the following input levels:  
LVCMOS or LVTTL  
TEST_CLK or CLK, nCLK inputs. The TEST_CLK input  
accepts LVCMOS or LVTTL input levels and translates them  
to 3.3V LVPECL levels.The CLK, nCLK pair can accept most  
standard differential input levels. The VCO operates at a  
frequency range of 250MHz to 700MHz.The VCO frequency  
is programmed in steps equal to the value of the input differ-  
ential or single ended reference frequency. The VCO and  
output frequency can be programmed using the serial or  
parallel interfaces to the configuration logic. The low phase  
noise characteristics of the ICS8432-101 makes it an ideal  
clock source for Gigabit Ethernet and SONET applications.  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
CLK, nCLK orTEST_CLK maximum input frequency: 40MHz  
Output frequency range: 25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
Accepts any single-ended input signal on CLK input  
with resistor bias on nCLK input  
Parallel interface for programming counter  
and output dividers  
RMS period jitter: 5ps (maximum)  
Cycle-to-cycle jitter: 25ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Lead-Free package fully RoHS compliant  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
CLK_SEL  
TEST_CLK  
0
32 31 30 29 28 27 26 25  
CLK  
nCLK  
1
M5  
M6  
M7  
M8  
N0  
N1  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
CLK  
TEST_CLK  
CLK_SEL  
VCCA  
ICS8432-101  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
PHASE DETECTOR  
MR  
0
VEE  
÷1  
÷2  
÷4  
÷8  
VCO  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
9
10 11 12 13 14 15 16  
÷ M  
1
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N1  
Y Package  
TopView  
8432DY-101  
www.icst.com/products/hiperclocks.html  
REV. B JUNE 1, 2005  
1

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