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ICS8430BI-71L PDF预览

ICS8430BI-71L

更新时间: 2024-11-02 11:14:39
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
16页 167K
描述
700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8430BI-71L 数据手册

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PRELIMINARY  
ICS8430BI-71  
Integrated  
Circuit  
Systems, Inc.  
700MHZ, LOW JITTER, CRYSTAL INTERFACE/  
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8430BI-71 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs  
ICS  
HiPerClockS™  
put Crystal/LVCMOS-to-3.3V Differential LVPECL  
Selectable crystal oscillator interface  
or LVCMOS TEST_CLK  
High Frequency Synthesizer and a member of the  
HiPerClockSfamily of High Performance Clock  
Solutions from ICS.The ICS8430BI-71 has a se-  
Output frequency up to 700MHz  
lectable crystal oscillator interface or LVCMOS TEST_CLK.  
The VCO operates at a frequency range of 250MHz to  
700MHz. With the output configured to divide the VCO  
frequency by 2, output frequency steps as small as 2MHz  
can be achieved using a 16MHz crystal or test clock. Output  
frequencies up to 700MHz can be programmed using the  
serial or parallel interfaces to the configuration logic.The low  
jitter and frequency range of the ICS8430BI-71 make it an  
ideal clock generator for most clock tree applications.  
Crystal input frequency range: 12MHz to 27MHz  
VCO range: 250MHz to 700MHz  
Parallel or serial interface for programming counter  
and output dividers  
RMS period jitter: 9ps (maximum)  
Cycle-to-cycle jitter: 25ps (maximum)  
3.3V supply voltage  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
32 31 30 29 28 27 26 25  
M5  
M6  
M7  
M8  
N0  
N1  
N2  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL_OUT  
TEST_CLK  
XTAL_SEL  
VCCA  
TEST_CLK  
0
1
XTAL_IN  
ICS8430BI-71  
OSC  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
XTAL_OUT  
÷ 16  
VEE  
9
10 11 12 13 14 15 16  
PLL  
PHASE DETECTOR  
0
1
VCO  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
MR  
÷ N  
32-Lead LQFP  
÷ M  
7mm x 7mm x 1.4mm package body  
÷ 2  
Y Package  
TopView  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
M0:M8  
N0:N2  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8430BYI-71  
www.icst.com/products/hiperclocks.html  
REV.A FEBRUARY 17, 2006  
1

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