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ICS8430AY-51 PDF预览

ICS8430AY-51

更新时间: 2024-11-02 11:14:39
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
16页 149K
描述
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8430AY-51 数据手册

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PRELIMINARY  
ICS8430-51  
Integrated  
Circuit  
Systems, Incꢀ  
600MHZ, LOW JITTER  
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8430-51 is a general purpose, dual output Dual differential 3.3V LVPECLoutputs  
Crystal-to-3.3V Differential LVPECLHigh Frequency  
Selectable crystal oscillator interface  
HiPerClockS™  
Synthesizer and a member of the HiPerClockS™  
or LVCMOS/LVTTL TEST_CLK  
family of High Performance Clock Solutions from  
ICS. The ICS8430-51 has a selectable TEST_CLK  
Maximum output frequency: 600MHz  
Crystal input frequency range: 14MHz to 25MHz  
VCO range: 200MHz to 700MHz  
or crystal inputs. The VCO operates at a frequency range of  
200MHz to 700MHz. With FOUT0 configured to divide the  
VCO frequency by 2, output frequency steps as small as  
2MHz can be achieved using a 16MHz crystal or reference clock.  
FOUT1 provides an additional divide by 16 and 180° phase shift.  
Output frequencies up to 600MHz can be programmed using  
the serial or parallel interfaces to the configuration logic. The low  
jitter and frequency range of the ICS8430-51 make it an ideal  
clock generator for most clock tree applications.  
Parallel or serial interface for programming counter  
and output dividers  
RMS period jitter: 2.6ps (typical)  
Cycle-to-cycle jitter: 17ps (typical)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
32 31 30 29 28 27 26 25  
TEST_CLK  
0
M5  
M6  
M7  
M8  
N0  
N1  
N2  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL1  
XTAL1  
1
TEST_CLK  
XTAL_SEL  
VCCA  
OSC  
XTAL2  
÷ 16  
ICS8430-51  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
PHASE DETECTOR  
VEE  
0
1
9
10 11 12 13 14 15 16  
MR  
VCO  
FOUT0  
nFOUT0  
FOUT1  
÷ N  
÷ M  
÷ 2  
nFOUT1  
÷16  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
M0:M8  
N0:N2  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8430AY-51  
www.icst.com/products/hiperclocks.html  
REV. D FEBRUARY 11, 2003  
1

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