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ICS843020AY-01LF PDF预览

ICS843020AY-01LF

更新时间: 2024-11-02 11:14:39
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
20页 216K
描述
FEMTOCLOCKS-TM 680MHZ, CRYSTAL-TO- 3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS843020AY-01LF 数据手册

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ICS843020-01  
FEMTOCLOCKS680MHZ, CRYSTAL-TO-  
3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS843020-01 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs  
ICS  
put Crystal-to-3.3V Differential LVPECL High Fre-  
Selectable crystal oscillator interface  
or LVCMOS/LVTTLTEST_CLK  
HiPerClockS™  
quency Synthesizer and a member of the  
FemtoClocksfamily of High Performance Clock  
Solutions from ICS. The ICS843020-01 is based  
Output frequency range: 70MHz to 680MHz  
Crystal input frequency range: 12MHz to 32MHz  
VCO range: 560MHz to 680MHz  
on ICS’ 3rd generation VCO technology and is capable of sub-  
1ps RMS Phase Jitter performance, making it ideal for use in  
10 Gigabit Ethernet, 10 Gigabit Fibre Channel, SONET and  
Serial ATA applications.  
Parallel or serial interface for programming feedback  
and output dividers  
The ICS843020-01 is a highly flexible programmable synthe-  
sizer capable of generating output frequencies over a range of  
70MHz to 680MHz.The output frequency can be programmed  
in small step sizes as low as 250kHz when using a 16MHz  
crystal, ÷8 input divider, and output divider = ÷8.  
Input P_DIV under parallel load control  
RMS phase jitter at 156.25MHz (1.875MHz to 20MHz):  
0.49ps (typical), P_DIV = ÷1  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Lead-Free package fully RoHS compliant  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
TEST_CLK  
0
XTAL_IN  
1
OSC  
32 31 30 29 28 27 26 25  
XTAL_OUT  
÷ P  
M5  
M6  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL_OUT  
TEST_CLK  
XTAL_SEL  
VCCA  
0
÷8  
P_DIV  
Float ÷1 (default)  
÷4  
1
M7  
M8  
ICS843020-01  
10 11 12 13 14 15 16  
32-Lead LQFP  
N0  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
N1  
÷N  
PHASE DETECTOR  
P_DIV  
÷ 1  
÷ 2  
÷ 4  
÷ 8  
MR  
0
1
VEE  
VCO  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
9
÷ M  
S_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
S_DATA  
S_CLOCK  
nP_LOAD  
TEST  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N1  
Y Package  
TopView  
843020AY-01  
www.icst.com/products/hiperclocks.html  
REV. B APRIL 14, 2005  
1

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